Stress Reduction Zone for IC Delamination Prevention
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Solution Overview
Problem
Integrated circuits with certain ultra-low K dielectric materials experience structural failure, including delamination, due to mismatch in coefficients of expansion between the chip and the module or package, particularly under C4 bond pads.
Innovation Solution
Incorporating elongated fill wires in the dielectric layers under C4 bond pads, which are not connected to operational wires or connected only to the ground network, to create a stress reduction zone and physically connect between interconnect levels, thereby reinforcing the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ultra-low K dielectric materials are used in interconnect levels, then signal delay is reduced, but structural failure and delamination occur due to thermal expansion mismatch
Solution Approach 1:
The patent applies local quality by creating a stress reduction zone with specific material properties around the C4 bond pad perimeter, while maintaining the ultra-low K dielectric material in other regions. This localized modification allows the dielectric to maintain its low signal delay properties overall while providing targeted stress relief where thermal expansion mismatch causes delamination.
Solution Approach 2:
The patent uses composite materials by combining the ultra-low K dielectric material with a stress reduction zone material that has different mechanical properties. This composite structure allows the system to benefit from the low signal delay of the ultra-low K material while the composite nature provides thermal stress management and prevents delamination.
2Adaptability or versatility
If C4 bond pads are used for interconnection, then connectivity is achieved, but delamination occurs under the bond pads due to coefficient of expansion mismatch
Solution Approach 1:
The patent implements local quality by creating a stress reduction zone with distinct material properties surrounding the C4 bond pad perimeter. This localized region provides targeted protection against delamination caused by thermal expansion mismatch, while the rest of the bond pad maintains its connectivity function.
Solution Approach 2:
The stress reduction zone acts as a beforehand cushioning mechanism by being pre-positioned around the C4 bond pad perimeter. This zone compensates for thermal stress before delamination can occur, cushioning the bond pad against the harmful effects of coefficient of expansion mismatch during thermal cycling.
3Speed
If dielectric layers are formed from certain materials to reduce signal delay, then speed is improved, but structural failure occurs under bond pads
Solution Approach 1:
The patent applies local quality by maintaining ultra-low K dielectric material in regions where signal delay reduction is critical, while introducing a stress reduction zone with enhanced mechanical properties around the C4 bond pad perimeter. This spatial differentiation allows the structure to have both high speed performance and localized structural strength.
Solution Approach 2:
The patent employs composite materials by combining ultra-low K dielectric material with a stress reduction zone material that has superior mechanical strength. This composite approach allows the interconnect structure to achieve both fast signal propagation and resistance to structural failure under bond pads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces or prevents delamination of ultra-low K dielectric layers, enhancing the structural integrity of integrated circuits by providing a stress reduction mechanism that aligns with the thermal expansion of the chip and package.
Implementation Method 1
mismatch in coefficients of expansion between the chip and the module or package
Implementation Method 2
create a stress reduction zone surrounding a perimeter of the bonding pad
Data Source
AI summary
An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.