Integrated Circuit Stress Prediction and Reliability Analysis
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in managing stresses and strains within integrated circuits, leading to issues such as gate oxide failure, increased leakage current, and reliability problems due to the thinning of gate oxides and silicon films, as well as mechanical stress from thermal expansion mismatch and processing techniques, which conventional stress analysis methods inadequately address.
Innovation Solution
A method and system that evaluate stresses among various layers of an integrated circuit using actual layout and process models to predict design criteria, incorporating concurrent models for manufacturing processes and techniques to compute non-planarity and accurately determine geometric and electrical characteristics, thereby addressing the root causes of stress-induced problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate oxide thickness is reduced to improve timing and reduce capacitance, then timing performance is improved, but oxide tunneling leakage current increases
Solution Approach 1:
The patent applies parameter changes by modifying the gate oxide thickness to optimize the balance between timing performance and leakage current. By carefully controlling the oxide thickness parameter within specific ranges, the invention achieves improved timing while managing tunneling leakage through precise parameter selection and process control.
2Speed
If thinner silicon films are used to reduce junction capacitance, then timing performance is improved, but body resistance increases and Joule heating worsens
Solution Approach 1:
The patent addresses this contradiction by optimizing the silicon film thickness parameter to achieve the desired balance. Through precise control of the silicon layer thickness and integration with stress management techniques, the invention reduces junction capacitance for improved timing while managing body resistance and Joule heating effects.
3Ease of manufacture
If conventional stress analysis methods are used, then manufacturing process is simple, but stress-induced problems such as gate oxide failure and reliability issues are not adequately addressed
Solution Approach 1:
The patent applies segmentation by dividing the stress analysis into multiple components: mechanical stress from thermal expansion mismatch, electrical stress from electric fields, and stress from processing techniques. This segmented approach allows comprehensive reliability assessment while maintaining manageable manufacturing processes through systematic evaluation of each stress component.
Solution Approach 2:
The invention implements preliminary action by performing comprehensive stress analysis during the design phase rather than relying solely on post-fabrication testing. By evaluating mechanical, electrical, and processing-induced stresses beforehand, the patent enables proactive design modifications to prevent gate oxide failure and reliability issues before manufacturing.
4Reliability
If redundant vias are added to address tensile stress and electro-migration, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent addresses this contradiction by optimizing via design parameters such as dimensions, material composition, and stress compensation structures. Through careful parameter selection and integration with layout design, the invention achieves improved via reliability against tensile stress and electro-migration while minimizing the increase in device complexity through efficient via placement and design rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise prediction and management of stresses and strains, improving the reliability and manufacturability of integrated circuits by accurately analyzing geometric and electrical characteristics, reducing the likelihood of failure and enhancing performance.
Implementation Method 1
the electric stress in the gate oxide caused by the electric field across the oxide has been shown to increase as the voltage drop across the oxide increases
Implementation Method 2
the stress also increases as the temperature rises due to Joule heating
Implementation Method 3
thinner gate oxide layer increases the oxide tunneling leakage current. It has been shown that the oxide tunneling leakage current increases roughly two and half times for every 0.1 nm reduction in oxide thickness
Implementation Method 4
thinner silicon films have shown to improve performance by reducing junction capacitance, but such films also cause the body resistance to degrade and worsens Joule heating
Implementation Method 5
The tensile stresses may cause stress-induced void nucleation and growth and therefore increase resistance and thus Joule heating which further worsens the electro-migration due to higher metal-ion diffusion
Implementation Method 6
the mechanical stress caused by thermal expansion mismatch among different materials within the stack or by other processing steps can also cause reliability or manufacturability problems in the vias
Implementation Method 7
various plasma enhanced deposition processes may cause electric stresses (plasma-induced damage) that may consume the life of the gate oxides or cause drifts in the MOSFET parameters
Implementation Method 8
In chemical-mechanical polishing, it has been shown that the flow stress of the copper film increases with the copper film thickness after the CMP planarization process
Data Source
AI summary
Disclosed is an improved method, system, and computer program product for predicting and improving the integrity, manufacturability, reliability, and performance of an electronic circuit feature based on the stresses or strains of design features of electronic designs. Some embodiments identify the design, the concurrent model(s), design feature physical or electrical parameters or attributes, analyzes the stresses or strains to predict the integrity of the design and determines whether the design meets the design objectives or constraints. Some other embodiments make corrections to the designs or the processes based upon the determination of whether the design meets the design objectives or constraints. Some other embodiments compute the variations of the design features as a result of the stresses or strains and determine their impact on the subsequent processes.