IC Substrate Manufacturing via Coupled Intermediate Substrates
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Solution Overview
Problem
In integrated circuit (IC) packaging, the thick core dielectric layer causes significant signal degradation, leading to wastage of metal layers in package-on-package and stacked die devices, as sensitive signals cannot be effectively passed through, resulting in underutilization of metal layers.
Innovation Solution
A manufacturing process is developed to form two substrates from what would typically be a single substrate, utilizing the metal layers on both sides of the core dielectric to increase substrate yield and reduce waste by coupling and separating intermediate substrates during production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick core dielectric layer is used in the substrate, then mechanical strength and structural stability are improved, but signal degradation increases and metal layers become wasted
Solution Approach 1:
The substrate manufacturing process is segmented into multiple stages with an intermediate substrate that can be coupled to another substrate. This segmentation allows the thick core dielectric to be divided into two functional parts, each on separate substrates that are coupled together, thereby reducing the effective signal path through the thick dielectric while maintaining its mechanical support function.
Solution Approach 2:
The solution transitions from a single-substrate vertical architecture to a multi-substrate coupled architecture. By stacking multiple substrates and coupling them through intermediate layers, the patent creates a three-dimensional structure that reduces signal degradation through the core dielectric while maintaining mechanical strength.
2Adaptability or versatility
If metal layers are formed on both sides of the core dielectric, then substrate functionality is improved, but signal degradation causes the metal layers on one side to be wasted
Solution Approach 1:
The substrate is segmented into multiple independent substrates, each utilizing the metal layers on their respective sides. By coupling these substrates together through intermediate layers, the patent ensures that metal layers on both sides of what would be a single thick dielectric are fully utilized for interconnections, eliminating waste.
Solution Approach 2:
The coupled substrate structure enables both substrates to serve functional interconnection purposes. The metal layers on both sides of the coupled structure are utilized for different interconnection functions, transforming the wasted metal layers into useful interconnection resources.
3Ease of operation
If signals are passed through the thick core dielectric using vias, then interconnection between metal layers is achieved, but signal quality degrades significantly
Solution Approach 1:
The single long via path through the thick core dielectric is segmented into multiple shorter via paths across coupled substrates. Each substrate has its own via structures that are shorter and maintain better signal quality, while the coupled substrates collectively provide the interconnection function.
4Ease of manufacture
If only one substrate is manufactured at a time, then manufacturing simplicity is maintained, but substrate yield is reduced due to wasted metal layers
Solution Approach 1:
The patent merges the manufacturing of multiple substrates by coupling intermediate substrates together during the manufacturing process. This allows metal layers that would be wasted on one substrate to be utilized in another substrate, effectively doubling the useful output without significantly complicating the manufacturing process.
Data Source
AI summary
Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).