IC Modeling with Substrate Harmonic Distortion Netlists
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Solution Overview
Problem
Current integrated circuit performance modeling techniques fail to adequately account for substrate-generated signal distortions, particularly substrate-generated harmonic signal distortions, which can impact signal integrity and violate FCC regulations on harmonics generation in radio applications.
Innovation Solution
A method and system that perform a parasitic extraction process to generate a layout-extracted netlist, which includes signal distortion models specific to circuit elements, accounting for substrate-generated signal distortions such as harmonic distortions, by analyzing the IC design layout and incorporating empirically determined level-specific signal distortion models into the netlist for simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current integrated circuit performance modeling techniques are used, then the modeling process is simple and fast, but substrate-generated signal distortions are not adequately modeled
Solution Approach 1:
The patent segments the modeling process by separating linear parasitic extraction from non-linear substrate distortion modeling. The netlist is divided into standard components and substrate distortion components that are modeled independently using different techniques, allowing each to be optimized separately while maintaining overall accuracy.
Solution Approach 2:
The patent introduces an intermediary substrate distortion model that mediates between the standard netlist extraction process and the final performance analysis. This model acts as a bridge, taking standard netlist data and adding substrate distortion effects without requiring complete redesign of the existing extraction tools.
2Reliability
If substrate-generated signal distortions are included in the netlist extraction process, then signal integrity is improved, but the extraction process becomes more complex
Solution Approach 1:
The patent performs preliminary identification of substrate-affected circuit elements during the layout analysis phase, before full netlist extraction. This allows the extraction tool to pre-configure appropriate modeling parameters and methods for identified elements, streamlining the subsequent extraction process.
Solution Approach 2:
The patent changes the parameter representation for substrate-affected elements by introducing additional parameters specific to substrate distortion modeling (such as non-linear capacitance values and substrate coupling coefficients) while maintaining compatibility with standard netlist parameters for non-affected elements.
3Measurement precision
If level-specific signal distortion models are used for different circuit elements, then modeling precision is improved, but the model library size and selection complexity increase
Solution Approach 1:
The patent applies local quality by using different signal distortion models for different levels of the integrated circuit (e.g., different metal layers, polysilicon layers). Each level-specific model is optimized for the characteristics of that particular layer, improving accuracy while allowing the system to handle complexity through automated model selection based on element location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate modeling of substrate-generated signal distortions, enabling designers to meet performance specifications and comply with FCC limits on harmonics, thereby improving signal integrity and reducing interference between signals.
Implementation Method 1
harmonic signal distortions that occur at the output of signal wires within the metal levels or polysilicon (PC) level of the IC due to non-linear capacitive coupling with the semiconductor substrate
Implementation Method 2
non-linear resistance through the portion of the semiconductor substrate between the semiconductor devices
Data Source
AI summary
Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist. Simulations are subsequently performed using this netlist to generate a performance model for the IC.