Integrated Circuit Substrate Lamination for High-Frequency Applications
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Solution Overview
Problem
Existing integrated circuit package manufacturing methods, such as those described in U.S. Pat. No. 7,795,071, rely on molding technology that requires insulating materials to be infused or injected, which may not be efficient for encapsulating conductive layers effectively.
Innovation Solution
The introduction of a lamination method for encapsulating conductive layers using a dielectric layer, allowing for the partial or complete removal of a carrier and enabling internal and external deposition of conductive trace layers, thereby eliminating the need for molding technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If molding technology is used to encapsulate conductive layers, then encapsulation can be achieved, but the process becomes complex and less efficient
Solution Approach 1:
The patent extracts the encapsulation function from the complex molding process and implements it through a simpler lamination process using pre-formed dielectric layers, eliminating the need for molding equipment and insulating material infusion
Solution Approach 2:
The patent replaces the mechanical molding process with a lamination process that uses layered dielectric structures, substituting a complex mechanical system with a simpler layering and bonding approach
2Strength
If a thick dielectric layer is used for encapsulation, then structural support is improved, but the substrate thickness increases and miniaturization is hindered
Solution Approach 1:
The patent uses composite dielectric layers with reinforcing structures that provide high structural support with minimal thickness, combining multiple materials with complementary properties to achieve both strength and thinness
Solution Approach 2:
The patent employs thin dielectric film structures that provide adequate mechanical support while maintaining minimal thickness, using advanced thin-film technology to achieve the required strength-to-thickness ratio
3Productivity
If molding technology is used, then encapsulation can be achieved, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent performs preliminary preparation of dielectric layers and conductive trace patterns before final assembly, allowing parallel processing and reducing the overall manufacturing time compared to sequential molding operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thin, strong dielectric layer that supports the substrate with or without a carrier, enabling efficient encapsulation of conductive layers and providing two-sided electronic connections, suitable for high-frequency and low-noise applications.
Implementation Method 1
a dielectric layer encapsulating the internal conductive trace layers through a lamination process
Implementation Method 2
internal conductive trace layer formed by one or more internal conductive traces that is deposited through plating or printing of an electronically conductive material
Implementation Method 3
internal conductive trace layer formed by one or more internal conductive traces that is deposited through plating or printing of an electronically conductive material
Data Source
AI summary
An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.