Patterned Metal Layer Nesting in IC Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit (IC) substrates have a thick profile due to the space occupied by dielectric material between patterned metal layers, which hinders the miniaturization of portable electronic devices and reduces routing density and mechanical stability.
Innovation Solution
Incorporating a second patterned metal layer between a first patterned metal layer, separated by a thinner dielectric layer that conforms to the shape of the first layer, allowing for a non-conductive layer on top, which reduces substrate thickness and enhances electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is formed between patterned metal layers to provide electrical insulation, then electrical insulation is achieved, but substrate thickness increases
Solution Approach 1:
The patent transitions from a conventional planar layering approach to a three-dimensional configuration where a second patterned metal layer is formed within the dielectric layer between first and third metal layers. This vertical integration allows electrical insulation to be maintained through the dielectric material while reducing the overall substrate thickness by utilizing the third dimension for routing.
Solution Approach 2:
The second patterned metal layer is nested within the dielectric layer that separates the first and third metal layers. This nesting configuration allows multiple conductive layers to be integrated within the substrate thickness without proportionally increasing the overall thickness, as the nested layer shares the vertical space with the dielectric material.
2Reliability
If dielectric material occupies the space between patterned metal layers, then electrical insulation is provided, but routing density decreases
Solution Approach 1:
The invention utilizes the vertical dimension by forming a second patterned metal layer within the dielectric layer between first and third metal layers. This three-dimensional routing approach increases the number of available signal paths without increasing the lateral substrate area, thereby improving routing density while maintaining electrical insulation through the dielectric material.
3Ease of manufacture
If traditional photolithography layering is used to build IC devices, then manufacturing simplicity is maintained, but substrate thickness increases
Solution Approach 1:
The dielectric layer is formed over the first patterned metal layer before the second and third metal layers are added. This preliminary formation of the dielectric layer with the second metal layer's space already allocated allows subsequent layers to be integrated without requiring thickening the substrate structure, thereby maintaining manufacturing simplicity while achieving reduced thickness.
Data Source
AI summary
An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.