IC Substrate with Self-Aligned Non-Tapered Vias for Higher Trace Density
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Solution Overview
Problem
Current substrate manufacturing techniques limit the achievable density of traces in integrated circuits due to the presence of vias and capture pads, restricting the performance of circuit substrates.
Innovation Solution
The development of a substrate with non-tapered vias that are self-aligned, eliminating the need for oversized capture pads, allowing for a higher density of traces by using an electrolytic copper plating process with specific dry film resist elements and rate controlling additives to control the growth of vias and traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrate manufacturing techniques with tapered vias and capture pads are used, then via formation is straightforward, but the trace density is limited
Solution Approach 1:
The electrolytic copper plating process automatically forms vias with self-aligned constant cross-sectional shapes through the differential growth rates controlled by rate controlling agents. The via structure itself serves its own alignment function, eliminating the need for separate capture pad structures and enabling higher trace density while maintaining manufacturing precision.
Solution Approach 2:
The invention changes the plating parameters by introducing rate controlling agents that create different copper deposition rates in different regions (faster in via regions, slower in trace regions). This parameter change enables the formation of vias with constant cross-sectional shapes and self-alignment, directly resolving the contradiction between via formation precision and trace density.
2Reliability
If oversized capture pads are used to accommodate tapered vias, then via alignment is ensured, but the area available for traces is reduced
Solution Approach 1:
The via structure performs its own alignment function through self-aligned formation via electrolytic plating with rate controlling agents. The constant cross-sectional shape of the via automatically aligns with the underlying trace, eliminating the need for oversized capture pads and maximizing the area available for traces while ensuring via alignment reliability.
Solution Approach 2:
The invention extracts and eliminates the capture pad structure from the conventional via formation process. By using electrolytic plating with rate controlling agents, the via forms directly aligned with the trace without requiring a separate capture pad, thereby removing the area constraint while maintaining alignment reliability.
3Manufacturing precision
If electrolytic copper plating with rate controlling agents is used, then via and trace growth is controlled, but the process complexity increases
Solution Approach 1:
The invention modifies the plating bath composition by adding rate controlling agents that create differential copper deposition rates. This parameter change enables precise control of via and trace growth, achieving the desired constant cross-sectional via shapes and self-alignment. The increased process complexity is offset by the elimination of subsequent alignment and capture pad formation steps.
Solution Approach 2:
The invention merges the via formation and trace formation processes into a single electrolytic plating step with rate controlling agents. This combines multiple functions (via formation, trace formation, and alignment) into one process, reducing the number of separate manufacturing steps despite the increased complexity of the plating chemistry itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the density of traces in the substrate, enhancing input/output density and improving the overall performance of integrated circuit packages without the need for oversized capture pads.
Implementation Method 1
applying a voltage to the electrolytic copper composition to plate a copper layer in the patterned regions
Implementation Method 2
an electrolytic copper plating process with specific dry film resist elements and rate controlling additives to control the growth of vias and traces
Data Source
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AI summary
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.