Multilayer IC Substrate Embedded Stiffeners Prevent Warping
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Solution Overview
Problem
Advanced IC substrates, particularly in FCBGA and FCCSP formats, face challenges with warping due to lack of mechanical stiffness, especially during elevated temperature processing, which can lead to system failures and reduced yields in first and second level assembly processes, and existing coreless substrate technologies require external metal frames that occupy valuable space.
Innovation Solution
A multilayer electronic support structure with non-electronically functional elongated metallic constructional elements encapsulated within dielectric material, spanning across layers to provide mechanical stiffness and relieve residual stresses, allowing for planarity and preventing warping without the need for external stiffeners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If coreless substrate technologies are used to reduce thickness, then thermal impedance and inductance are improved, but mechanical stiffness deteriorates causing warping
Solution Approach 1:
The patent employs a composite structure combining dielectric material with embedded metallic constructional elements. The dielectric material provides electrical insulation and thermal management, while the metallic elements provide mechanical stiffness and warpage resistance. This composite approach allows the substrate to achieve both low thermal impedance and high mechanical stability without requiring a traditional core structure.
Solution Approach 2:
The patent introduces constructional elements that extend in the vertical dimension (Z-direction) through the dielectric layers, creating a three-dimensional reinforcement structure. These elements span multiple layers and provide stiffness throughout the substrate thickness, effectively preventing warping while maintaining the thin-profile advantage of coreless designs.
2Stability of the object's composition
If external metal frame stiffeners are added to maintain flatness, then warping is prevented, but available space for components is reduced
Solution Approach 1:
The constructional elements are nested within the dielectric material structure itself, embedded during the layer-by-layer fabrication process. This integration allows the stiffening function to be incorporated into the substrate's internal architecture rather than adding external frames, thereby preserving surface area for electronic components while maintaining substrate flatness.
Solution Approach 2:
The patent merges the structural reinforcement function with the electrical insulation function by integrating metallic constructional elements directly into the dielectric stack. This combination eliminates the need for separate external stiffeners and allows both mechanical support and electrical isolation to coexist within the same structural volume.
3Stability of the object's composition
If multilayer stack is built up on both sides to balance stresses, then warpage is reduced, but device complexity increases
Solution Approach 1:
The constructional elements are incorporated into the dielectric layers during the initial fabrication process, before the substrate undergoes subsequent processing and assembly steps. This preliminary integration ensures that stress-balancing structures are already in place to prevent warpage during later high-temperature processing, eliminating the need for complex post-fabrication adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances the mechanical stiffness of IC substrates, preventing warping and ensuring planarity, thereby improving the reliability of IC packages during assembly and operation, while maintaining a thin and efficient design that meets the demands of modern electronic devices.
Implementation Method 1
the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding
Implementation Method 2
fabricated using electroplating and photoresist techniques
Implementation Method 3
fabricated using electroplating and photoresist techniques
Data Source
AI summary
A multilayer electronic support structure including at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.