Master-Slave IC Synchronization via SYNC Bus Feedback
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Solution Overview
Problem
Existing methods for synchronizing integrated circuits, particularly in high-speed systems requiring functional safety, fail to adequately minimize synchronization delays, which can lead to safety risks due to inaccuracies in signaling between master and slave ICs.
Innovation Solution
A method involving a master IC sending a pulse over a SYNC bus to a slave IC, receiving and checking a response pulse, triggering an interrupt if failure is detected, and initiating measurement for synchronization, utilizing a bidirectional single wire interface and phase-locked-loop generated clock signals to ensure accurate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional synchronization methods are used between master and slave ICs, then basic synchronization functionality is achieved, but synchronization delay cannot be adequately minimized
Solution Approach 1:
The patent measures and determines the propagation delay between master and slave ICs in advance during an initialization phase. This preliminary measurement allows the system to pre-calculate compensation values that are stored and applied during subsequent synchronization operations, eliminating the need for real-time delay calculation and minimizing synchronization delay while maintaining accuracy
Solution Approach 2:
The patent implements a feedback mechanism where the slave IC sends acknowledgment signals back to the master IC, and the master IC adjusts its timing based on the measured propagation delay and received acknowledgments. This closed-loop feedback system continuously optimizes synchronization timing, ensuring both minimal delay and high reliability in signaling accuracy
2Speed
If high-speed operation is implemented in integrated circuits, then processing speed is improved, but synchronization accuracy between ICs deteriorates
Solution Approach 1:
The patent employs periodic synchronization pulses and acknowledgment signals exchanged between master and slave ICs. By using regularly timed periodic signals rather than continuous communication, the system maintains synchronization accuracy even at high clock rates, as each periodic exchange provides a fresh timing reference that compensates for high-speed variations
Solution Approach 2:
Before high-speed data transmission begins, the system performs preliminary timing calibration by measuring propagation delays and establishing reference timing relationships. This preliminary setup creates a synchronized foundation that allows subsequent high-speed operations to maintain accuracy without requiring continuous adjustment during data transmission
Data Source
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AI summary
In accordance with aspects of the present invention, a method of synchronizing two integrated circuits is presented. A method of synchronizing two integrated circuits can include sending a first pulse from a master IC to a slave IC over a SYNC bus; receiving a second pulse on the SYNC bus from the slave IC; checking the second pulse; triggering an interrupt if a failure is detected; and initiating measurement if synchronization is detected.