Integrated IC Synthesis and Formal Verification
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Solution Overview
Problem
The existing approach to designing integrated circuits (ICs) involves separate and sequential steps for synthesis and formal verification, leading to inefficiencies, such as back-and-forth discussions, misunderstandings, and increased verification time, as different teams handle these processes without expertise in both areas, often resulting in failed verification and time-consuming validation.
Innovation Solution
A framework that performs synthesis and formal verification simultaneously or in an interleaved manner, using a single interface to automatically verify intermediate netlists, allowing for incremental checks and providing options for fixing issues, with the ability to integrate simulation-based verification when necessary, utilizing tools like OneSpin® and Formality®, and allowing multiple verification tools to run concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate and sequential steps for synthesis and formal verification are used, then different teams can handle these processes independently, but verification time increases and verification success rate decreases due to back-and-forth discussions and misunderstandings
Solution Approach 1:
The patent combines synthesis and formal verification into a single integrated process that operates simultaneously rather than sequentially. The formal verification unit is integrated into the synthesis flow, allowing both operations to proceed in parallel and share intermediate results, thereby reducing total verification time and improving success rates through continuous feedback.
Solution Approach 2:
The patent performs preliminary formal verification checks at intermediate stages during the synthesis process, rather than waiting for complete synthesis. This allows early detection of verification issues and enables corrective actions to be taken during synthesis rather than after, preventing wasted time on fundamentally flawed designs.
2Ease of operation
If separate teams handle synthesis and formal verification, then specialization is maintained, but communication overhead and misunderstandings increase leading to increased verification time
Solution Approach 1:
The patent merges the formal verification function into the synthesis tool itself, creating a unified system where both functions are managed by a single interface and control flow. This eliminates the need for separate teams to coordinate and exchange files, directly reducing communication overhead and verification time.
3Use of energy by moving object
If sequential synthesis and verification are performed, then resource usage is manageable, but total design cycle time increases due to waiting periods
Solution Approach 1:
The patent implements a dynamic resource management system that monitors computational resource availability during the integrated synthesis and verification process. When resources are available, verification operations are executed in parallel with synthesis; when resources are constrained, the system dynamically adjusts the verification schedule to prevent resource exhaustion, thereby maintaining high resource utilization while minimizing design cycle time.
Data Source
AI summary
A technology is described for designing an integrated circuit (IC) by incrementally and concurrently synthesizing and formally verifying a plurality of intermediate netlists. The intermediate netlists are synthesized from a register transfer level (RTL) description of the IC. Synthesizing intermediate netlists is continued while the formal verification processes execute concurrently with the synthesizing. An indication of validity or non-validity of the intermediate netlists is from the formal verification process. The RTL description is proven to be formally equivalent to a final netlist formed of the intermediate netlists by proving that the all the intermediate netlists are valid.