Integrated Circuit Test Cell Placement via Die Area Segmentation
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Solution Overview
Problem
In advanced technology nodes, such as the 28 nm node and below, the limited space between circuit features in integrated circuits poses a challenge for incorporating test cells into layouts, especially in middle-of-line layers like the via-zero layer, which hampers the inclusion of necessary test features for monitoring and process optimization.
Innovation Solution
A method is introduced to partition the die area of integrated circuits into tiles, determining available spaces for test cells and dummy cells within each layer, and strategically including them based on space availability criteria, ensuring that constraints related to feature separation and open circuits are met, thereby allowing for the inclusion of test cells and dummy cells in layers like the via-zero layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the die area is fully utilized for functional circuit features, then the manufacturing efficiency and productivity are improved, but the space available for test cells and dummy cells is reduced
Solution Approach 1:
The die area is divided into multiple tiles, each independently evaluated for space availability. This segmentation allows systematic identification of suitable locations for test cells without compromising overall functional circuit density, resolving the conflict between maximizing productivity and maintaining space for test features.
Solution Approach 2:
The method performs preliminary determination of space availability for test cells and dummy cells before final layout completion. By evaluating each tile's space capacity in advance and strategically placing test features, the methodology ensures both functional circuit density and test cell inclusion are optimized, addressing the contradiction between manufacturing efficiency and test space requirements.
2Reliability
If test cells are included in middle-of-line layers, then process monitoring capability is improved, but the layout complexity and device complexity increase
Solution Approach 1:
Test cells and dummy cells are selectively placed in specific tiles where space availability criteria are met, rather than uniformly distributed. This localized approach enables process monitoring in critical middle-of-line layers while maintaining simpler layouts in areas where test features are not required, thus improving reliability without excessively increasing overall layout complexity.
Solution Approach 2:
The methodology performs preliminary evaluation of each tile's space availability and suitability for test cells before final placement. This advance planning allows strategic insertion of test features in middle-of-line layers to enhance process monitoring, while avoiding unnecessary complexity in regions where test cells cannot be accommodated.
3Area of stationary object
If the density of circuit features is increased, then the area utilization is improved, but the manufacturability and ease of manufacture deteriorate
Solution Approach 1:
By dividing the die area into tiles and evaluating each independently, the methodology identifies optimal locations for test cells and dummy cells that maintain appropriate feature density. This segmentation ensures high area utilization for functional circuits while preserving manufacturability by preventing excessive density in any single region.
Solution Approach 2:
The methodology adjusts the density parameters of circuit features by strategically placing dummy cells in tiles with available space. This controlled modification of density parameters maintains high overall area utilization while ensuring manufacturability is preserved through appropriate feature distribution across different tiles.
Data Source
AI summary
A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.