Integrated Circuit Test Sequencing via Dynamic Control Value Selection
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Solution Overview
Problem
Traditional built-in self-test circuits in integrated circuits are complex, vulnerable to noise, require significant space, and offer only stereotypical test sequences, limiting their ability to provide accurate and varied test operations.
Innovation Solution
An integrated circuit configuration that includes a test counting circuit, a test information storage circuit, and a sequence control circuit, allowing for the generation of various test sequences and the ability to change test control values to target control values in case of errors, enabling more flexible and precise test operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a built-in self-test circuit is implemented to reduce testing time and cost, then productivity improves, but device complexity increases
Solution Approach 1:
The test information storage circuit is designed to store multiple types of test control values (first, second, and third test control values) that can be selectively output based on different test conditions. This multi-functionality allows a single circuit to perform various test operations, improving productivity while managing complexity through versatile design rather than multiple separate circuits.
Solution Approach 2:
The patent implements dynamic selection of test control values based on test clock cycles and control signals. The circuit can switch between different test control values (first, second, third) depending on the test phase and requirements, allowing the system to adapt its behavior dynamically. This dynamic operation enables comprehensive testing capabilities while maintaining a relatively compact circuit structure.
2Productivity
If a built-in self-test circuit is implemented to reduce testing time and cost, then productivity improves, but reliability deteriorates due to noise vulnerability
Solution Approach 1:
The test control mechanism is segmented into multiple independent test control values (first, second, third test control values) stored in the test information storage circuit. Each test control value can be independently selected and applied based on specific test conditions. This segmentation isolates different test functions, reducing the propagation of noise effects and improving reliability while maintaining high productivity through efficient test sequencing.
Solution Approach 2:
The patent incorporates control circuits that monitor test conditions and selectively output appropriate test control values based on feedback from the testing process. The control logic adjusts which test control value is applied based on the current test phase and detected conditions, creating a feedback mechanism that enhances reliability by selecting the most appropriate test parameters while maintaining fast testing throughput.
3Productivity
If a built-in self-test circuit is implemented to reduce testing time and cost, then productivity improves, but area occupied increases
Solution Approach 1:
The patent combines multiple test control value storage functions into a single test information storage circuit. Instead of implementing separate circuits for different test operations, the design merges first, second, and third test control values into one unified storage structure that can be selectively accessed. This merging approach maintains comprehensive testing capabilities while significantly reducing the total area occupied compared to multiple separate circuits, thus improving productivity without proportionally increasing area.
4Device complexity
If only stereotypical test sequences are provided, then device complexity is reduced, but adaptability deteriorates
Solution Approach 1:
The test sequence is made dynamic through the selective output of different test control values based on test clock cycles and control signals. The circuit can transition between first, second, and third test control values depending on the testing phase and requirements. This dynamic capability provides high adaptability for various test scenarios while maintaining relatively simple circuit architecture, resolving the contradiction between complexity and versatility.
Solution Approach 2:
The patent changes test parameters by selecting different test control values from the storage circuit based on test conditions. By varying which test control value is applied (first, second, or third), the system adapts to different test requirements without requiring complex reconfiguration circuits. This parameter change approach enables versatile testing capabilities while keeping the overall device complexity manageable.
Data Source
AI summary
An integrated circuit includes a test counting circuit, a test information storage circuit, a sequence control circuit and a driving circuit. The test counting circuit generates a counting address signal. The test information storage circuit stores a test control value and outputs the test control value based on the counting address signal. The sequence control circuit changes an output sequence of the test control value based on a sequence control signal and outputs a final test control value based on the test control value or a target control value. The driving circuit performs a pre-set test operation based on the final test control value.