Integrated Circuit Test Escape Rate Estimation
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Solution Overview
Problem
Current methods for estimating test escape rates in integrated circuit (IC) testing are limited by their unidimensional approach, neglecting overlapping fault detection capabilities of multiple test types, which complicates trade-off analysis and optimization of test generation efforts.
Innovation Solution
A system and method that combines failure data and fault coverage data from multiple tests to estimate a test escape rate, considering the overlapping nature of test sets, using a fault data processor and combined coverage generator to generate a combined coverage for tests of interest, and a defect level calculator to estimate the test escape rate based on yield and fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test types are used to improve fault coverage, then test coverage increases, but test complexity and resource requirements increase
Solution Approach 1:
The patent combines multiple test types (ATPG tests, fault simulation tests, transition tests, IDDQ tests) into a unified test program with integrated fault coverage analysis. The system merges test data from different sources and applies comprehensive mathematical models to evaluate overall fault coverage, thereby achieving high reliability without proportionally increasing test complexity through systematic integration.
Solution Approach 2:
The patent creates a universal test framework that can handle multiple test types and fault models through a single integrated system. The mathematical models and analysis methods are designed to be applicable across different test scenarios, allowing the same infrastructure to evaluate various test combinations and provide comprehensive fault coverage assessment.
2Ease of operation
If conventional unidimensional models are used, then estimation simplicity is maintained, but accuracy of test escape rate estimation deteriorates
Solution Approach 1:
The patent transitions from unidimensional test escape rate models to multidimensional models that simultaneously consider multiple test types, their overlapping fault detection capabilities, yield data, and fault coverage metrics. This dimensional expansion enables comprehensive analysis of how different tests interact and contribute to overall defect detection, significantly improving estimation accuracy while maintaining systematic evaluation through integrated mathematical frameworks.
3Reliability
If high fault coverage is achieved through careful DFT implementation, then test coverage improves, but design cost and test generation time increase
Solution Approach 1:
The patent performs preliminary fault coverage analysis and test escape rate estimation during the design phase using mathematical models. By evaluating different test combinations and their expected effectiveness beforehand, designers can make informed decisions about test program composition before actual test generation, avoiding unnecessary test generation time and resource expenditure while achieving target fault coverage levels.
Data Source
AI summary
A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.