IC Test Method Using IDDQ Data Reordering for Defect Detection
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Solution Overview
Problem
Conventional IC tests, such as quiescent DC current (IDDQ) tests, struggle to accurately distinguish between normal and defective ICs due to reduced IDDQ values as IC scales decrease, leading to unreliable delta IDDQ analysis with random or unsorted distributions.
Innovation Solution
An IC test method that generates and reorders IDDQ data using N test patterns, calculates reference values and orders test patterns, and determines chip defectivity based on IDDQ ranges, ensuring reliable differentiation between normal and defective ICs by analyzing delta IDDQ distributions and adjusting for dominant test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional IDDQ test is used to test scaled-down ICs, then the test process remains simple, but the measurement precision deteriorates because reduced IDDQ values look like general leakage current and cannot be accurately distinguished between normal and defective ICs
Solution Approach 1:
The patent segments the test process by dividing test patterns into ordered sequences and segmenting IDDQ measurements into grouped comparisons. Instead of treating all measurements equally, the patent groups measurements by test pattern order and compares within groups, thereby improving precision without proportionally increasing overall test complexity.
Solution Approach 2:
The patent changes the parameter of test pattern ordering by sorting test patterns according to their reference values. This parameter change transforms random or unsorted test pattern sequences into ordered sequences, enabling more reliable delta IDDQ analysis and improving measurement precision for detecting defective ICs.
2Reliability
If delta IDDQ analysis is performed using random or unsorted test patterns, then the test coverage is comprehensive, but the reliability deteriorates because the distribution of delta IDDQ values becomes random or unsorted, leading to false classifications
Solution Approach 1:
The patent performs preliminary sorting of test patterns according to reference values before conducting delta IDDQ analysis. This preliminary action ensures that test patterns are in the correct order, which is essential for reliable defect detection. The sorting is done once beforehand, avoiding the need for complex real-time ordering during analysis.
Solution Approach 2:
The patent uses reference values calculated from grouped measurements as feedback to determine the ordering of test patterns. These reference values guide the sorting process, creating a feedback loop where measurement results inform the structure of subsequent analysis, thereby improving reliability through data-driven ordering.
3Measurement precision
If multiple test patterns are applied to generate delta IDDQ distribution, then the defect detection capability is enhanced, but the false positive rate increases when dominant test patterns create unsorted distributions
Solution Approach 1:
The patent applies local quality by treating different groups of test patterns differently based on their reference values. Instead of uniform treatment, the patent creates localized groups of measurements associated with specific test patterns, allowing each group to be analyzed in its proper context. This local grouping approach improves defect detection accuracy while maintaining classification reliability.
Data Source
AI summary
The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.