IC Test Path Identification Using Multi-Cycle Capture Sequences
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Solution Overview
Problem
Conventional IC chip testing methods fail to adequately test longer and more critical paths, leading to unacceptably high failure rates due to time and effort constraints, and often incorrectly reject good products by testing functionally false paths.
Innovation Solution
The method involves using a timing tool to enumerate critical paths, identifying sequential functional paths through test sequences with multiple functional capture cycles, and employing launch-off-scan and launch-off-capture test sequences to generate and test these paths, thereby reducing test data volume and improving test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If transition fault test patterns are generated using the easiest and shortest paths through combinational logic, then test generation time and effort are reduced, but longer and more critical paths remain untested leading to high failure rates
Solution Approach 1:
The patent segments the testing process into two distinct phases: (1) testing of shorter combinational paths using conventional transition fault test patterns, and (2) testing of longer sequential paths using specially generated sequential test patterns. This segmentation allows each phase to use optimized methods appropriate to its specific requirements, resolving the contradiction between test time and coverage of critical paths.
Solution Approach 2:
The patent applies partial action by selectively testing only the most critical sequential paths rather than attempting to test all possible paths. The method identifies and prioritizes paths that are both long and critical to functional operation, testing a subset of paths that provides maximum reliability improvement with minimal additional test time.
2Reliability
If all longer critical paths are tested, then path coverage and reliability are improved, but test time and test generation effort become unmanageable
Solution Approach 1:
The patent implements partial action by selectively testing only the most critical sequential paths rather than all possible paths. The method identifies and prioritizes paths that are both long and critical to functional operation, testing a subset of paths that provides maximum reliability improvement with minimal additional test time.
Solution Approach 2:
The patent changes the testing parameters by transitioning from combinational test patterns to sequential test patterns, and from single-cycle testing to multi-cycle testing. These parameter changes enable effective testing of longer paths while maintaining manageable test times through optimized test sequence generation.
3Reliability
If functionally false paths are tested, then comprehensive path coverage is achieved, but good products are unnecessarily rejected
Solution Approach 1:
The patent applies preliminary action by identifying and classifying paths as functionally true or functionally false before test generation. This preliminary classification allows the testing process to focus only on functionally true paths, eliminating the possibility of falsely rejecting good products while maintaining comprehensive coverage of relevant paths.
Solution Approach 2:
The patent extracts and removes functionally false paths from the testing process entirely. By identifying paths that cannot be exercised during normal functional operation and excluding them from test generation, the method eliminates a major source of false failures while maintaining coverage of all functionally relevant paths.
Data Source
AI summary
A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.