Integrated Circuit Test Pattern Generation Using Weighted Net Segments
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Solution Overview
Problem
Conventional testing methodologies for integrated circuits focus on logic-level models, failing to comprehensively test physical design features and attributes, leading to undetected physical defects and difficulties in diagnosis.
Innovation Solution
A method that determines physical features and attributes of integrated circuits, assigns weights to net segments based on measurement units, and generates test patterns to maximize detection of these features, using a weighted test netlist independent of specific fault models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic-level testing methodologies are used, then testing process is simple and fast, but physical defects are not detected and test coverage is incomplete
Solution Approach 1:
The patent segments the integrated circuit into individual nets and further divides nets into segments with specific physical characteristics. By analyzing each net segment separately with assigned weights based on physical features (length, area, shape), the methodology achieves comprehensive physical defect detection while maintaining a systematic, manageable testing process that doesn't require complete methodological overhaul.
Solution Approach 2:
The patent transitions from conventional logic-level testing (functional dimension) to physical-level testing by incorporating spatial dimensions. Test patterns are generated based on physical net characteristics such as length, area, and shape factors, adding a physical dimension to the testing methodology that enables detection of physical defects invisible to logic-level testing.
2Measurement precision
If logic-level test models are used, then test generation is efficient, but physical design features are not adequately tested
Solution Approach 1:
The patent performs preliminary actions by pre-calculating physical characteristics of all nets (length, area, shape factors) and assigning weights to net segments before test pattern generation. This pre-processing step enables the subsequent test generation to focus specifically on physical defect detection without recalculation overhead, maintaining efficiency while achieving precise physical feature measurement.
Solution Approach 2:
The patent introduces an intermediary layer between logic-level testing and physical defect detection. Weighted net segment models serve as intermediaries that translate physical design features into testable parameters, allowing efficient test pattern generation that targets physical defects without requiring direct complex physical measurements during the testing process.
3Reliability
If comprehensive physical feature testing is implemented, then defect detection capability improves, but test complexity and computational requirements increase
Solution Approach 1:
The patent applies local quality by assigning different weights to different net segments based on their specific physical characteristics. Instead of uniform testing, each net segment is weighted according to its length, area, and shape factors, allowing the testing methodology to focus computational resources on segments with higher defect probability while maintaining comprehensive coverage.
Solution Approach 2:
The patent changes parameters by transforming physical net characteristics (length, area, shape) into weighted test priorities. By converting physical measurements into dimensionless weight factors that can be directly applied to test pattern generation, the methodology achieves comprehensive physical defect detection without requiring complex real-time physical measurements during test execution.
Data Source
AI summary
A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.


