IC Test Plan Optimization via Parallel Activity Execution
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Solution Overview
Problem
The existing methods for testing Integrated Circuits (ICs) are inefficient due to the significant impact of delay timings on total test time, which increases the cost and duration of testing, especially when testing multiple ICs.
Innovation Solution
A method that allows one or more activities to be performed during the desired wait time associated with parameter measurement, logging the delay time, and modifying the test sequence based on this time to optimize the test plan, thereby reducing overall test time and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay timings are inserted in the test plan to account for stabilizing time of measurement instruments and functional elements, then measurement reliability is improved, but total test time increases significantly
Solution Approach 1:
The patent merges multiple activities that were previously performed sequentially into parallel execution during delay periods. Specifically, it combines measurement activities, configuration activities, and data transfer activities to execute simultaneously during the stabilizing time of measurement instruments, thereby reducing total test time while maintaining measurement reliability
Solution Approach 2:
The patent eliminates idle delay periods by continuously utilizing the stabilizing time of measurement instruments to perform other useful activities. Instead of inserting empty delays, the system configures test parameters, performs measurements on other ICs, or transfers data during these periods, ensuring continuous productive action throughout the test process
2Reliability
If multiple ICs are tested using traditional test plans with delays, then comprehensive testing coverage is achieved, but the cost and time for testing the batch increases significantly
Solution Approach 1:
The patent creates a universal test plan structure that can be applied to batches of ICs with similar characteristics. By identifying common delay periods across multiple IC tests and performing standardized activities (such as instrument configuration and data transfer) during these delays, the system achieves multi-functionality that improves batch testing efficiency while maintaining comprehensive coverage
Solution Approach 2:
The patent performs preliminary configuration of test parameters and instruments during delay periods before actual measurements are required. This preliminary action prepares the test system in advance, reducing setup time for subsequent measurements on multiple ICs and improving overall batch testing productivity
Data Source
AI summary
A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.