Integrated Circuit Testing Scramble Equation Correction
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Solution Overview
Problem
The existing methods for testing integrated circuits are inefficient in identifying and correcting unfitted scramble equations, leading to distorted test graphs and increased time and error susceptibility during the development of new products, due to the manual analysis required for different electrical addresses and designs.
Innovation Solution
An integrated circuit testing method and apparatus that uses pattern recognition to introduce an original verification pattern during qualitative testing, convert raw data to a test graph using pre-determined scramble equations, and automatically correct these equations based on comparisons, thereby accurately identifying incorrect scramble equations and shortening the product verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual analysis is used to identify and correct unfitted scramble equations, then flexibility in handling different electrical addresses and designs is maintained, but the process becomes time-consuming and susceptible to errors
Solution Approach 1:
The patent replaces the manual mechanical analysis process with an automated computer-based system that uses algorithms to identify and correct unfitted scramble equations. The system automatically compares test graphs with expected patterns and detects discrepancies, eliminating the need for manual inspection while maintaining high accuracy and reducing time consumption.
Solution Approach 2:
The system enables self-correction of unfitted scramble equations by automatically detecting errors in the test graphs and generating corrected versions without human intervention. The automated process serves itself by identifying issues and applying corrections, thereby reducing both time and potential for human error.
2Adaptability or versatility
If manual analysis is used to convert test data with electrical addresses to test graphs with physical addresses, then adaptability to different product designs is maintained, but the process becomes error-prone and time-consuming
Solution Approach 1:
The patent replaces manual conversion processes with automated computer-based algorithms that systematically transform test data from electrical addresses to physical addresses. The automated system maintains adaptability to different product designs through configurable parameters while eliminating human errors in the conversion process.
Solution Approach 2:
The system incorporates feedback mechanisms that compare the converted test graphs with expected patterns and automatically detect discrepancies. This feedback loop ensures high measurement precision by validating the conversion process and correcting any errors that may occur during the transformation from electrical to physical addresses.
Data Source
AI summary
A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.