Programmable IC Test Sequence Ranking by Untested Arcs
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Solution Overview
Problem
The testing of routing resources in programmable logic devices like FPGAs is time-consuming and costly due to the vast number of possible routes, often exceeding the capacity of test tools to fully exercise all arcs in a single test sequence, especially as the complexity of these devices increases.
Innovation Solution
A method that generates a test sequence list ranking test patterns by the number of untested arcs, prioritizing those with the greatest number of untested arcs first, to improve the likelihood of detecting failures early in the testing process, using a ranking tool that compares each test design against a record of already-tested arcs and applies weighting factors based on failure likelihood.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all arcs in the routing fabric are tested using traditional test sequences, then complete coverage of routing resources is achieved, but test time becomes excessively long and costly
Solution Approach 1:
The patent applies preliminary action by generating a comprehensive list of all possible arc test patterns before the actual testing begins. This pre-generated test pattern library allows the testing system to quickly select and execute only the necessary test patterns based on device complexity and routing fabric size, rather than exhaustively testing all possible arcs. The test patterns are prepared in advance and stored for efficient retrieval during the actual testing phase, significantly reducing test time while maintaining adequate coverage.
Solution Approach 2:
The patent implements partial action by selecting and executing only a subset of test patterns from the comprehensive library, rather than running all possible arc tests. The system determines the appropriate level of testing based on device complexity metrics and routing fabric characteristics, performing enough testing to ensure reliability without the excessive time cost of complete exhaustive testing. This selective approach achieves the optimal balance between test coverage and test time.
2Adaptability or versatility
If the complexity of FPGAs increases to provide more routing resources, then device functionality and versatility improve, but the capacity of test tools to fully exercise all arcs is exceeded
Solution Approach 1:
The patent applies segmentation by dividing the comprehensive test pattern library into manageable segments or categories based on device complexity and routing fabric characteristics. The test patterns are organized in a structured manner that allows the testing system to efficiently select and execute only the relevant segments appropriate for the specific device being tested. This segmentation enables test tools to handle highly complex FPGAs by processing test patterns in organized groups rather than as an overwhelming monolithic set.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting test parameters such as the number of test patterns to execute, the depth of routing fabric testing, and the complexity level based on the specific device characteristics. The system modifies testing parameters according to device complexity metrics, routing fabric size, and available test resources, allowing the same test infrastructure to effectively handle devices ranging from simple to highly complex without exceeding tool capacity.
Data Source
AI summary
A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.