IC Test System Stage Wagon Docking Mechanism

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Solution Overview

Problem

The increased throughput in IC-level tests leads to heavier and more cumbersome burn-in boards, making transportation unstable and inefficient, with a high risk of collision and damage to the ICs during handling.

Innovation Solution

An integrated-circuit-level test system and method that uses a stage wagon to provide burn-in boards to an IC loading chamber, where the ICs are disposed according to specific configurations determined by docking mechanisms, and then transported to a test chamber for testing, allowing for efficient and stable handling of multiple boards at once.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the throughput of IC-level tests is increased, then the testing efficiency is improved, but the number and total weight of burn-in boards increases, making transportation unstable and prone to collision

Engineering Contradiction:
Improvetesting efficiencyVSAvoidtransportation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system divides burn-in boards into different groups based on their weight characteristics. Heavy boards are segmented and transported separately using specialized heavy-board carriers, while light boards use standard carriers. This segmentation prevents mixed loading that causes instability and collision during transportation, while still allowing high throughput by optimizing each segment's transport capacity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If more burn-in boards are transported simultaneously to increase throughput, then testing capacity is improved, but the risk of inclination and collision during transportation increases

Engineering Contradiction:
Improvetesting capacityVSAvoidrisk of inclination and collision
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system introduces docking mechanisms as intermediaries between the stage wagon and test chambers. These docking mechanisms provide stable coupling and precise positioning during board transfer, reducing the risk of inclination and collision. The docking mechanisms act as a buffer that absorbs transport uncertainties while maintaining high throughput capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary classification of burn-in boards by weight before transportation. Heavy boards are pre-identified and assigned to specialized carriers with enhanced stabilization features. This preliminary action prevents mixing of heavy and light boards during transport, eliminating the root cause of inclination and collision risks while maintaining high transport capacity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If heavy burn-in boards are transported together with light boards, then transportation efficiency is improved, but the stability during handling deteriorates due to weight differences

Engineering Contradiction:
Improvetransportation efficiencyVSAvoidhandling stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The system segments burn-in boards into heavy and light categories using weight detection mechanisms. Each category is transported in separate dedicated carriers optimized for its weight range. Heavy board carriers have reinforced structures and lower center of gravity design, while light board carriers use lighter materials. This segmentation maintains high transportation efficiency by optimizing each carrier's load capacity while ensuring handling stability through appropriate carrier-board matching.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11408931B1Integrated-circuit-level test system and method
Publication Date: 2022.08.09 NAN YA TECH
  • US11408931B1 patent drawing
  • US11408931B1 patent drawing
  • US11408931B1 patent drawing

AI summary

The present disclosure provides an integrated-circuit-level (IC-level) test method and system. The IC-level test method includes the operations of: providing, by a stage wagon, a plurality of burn-in boards to an IC loading chamber; determining, by the IC loading chamber, at least one disposing configuration for a plurality of ICs according to at least one docking mechanism of the stage wagon; disposing, by the IC loading chamber, the plurality of ICs on each of the plurality of burn-in boards according to the at least one disposing configuration; providing, by the stage wagon, the plurality of burn-in boards with the plurality of ICs to a test chamber; and performing, by the test chamber, a test function on the plurality of ICs to determine a status of each of the plurality of ICs.