Integrated Circuit Test Circuit Using Storage Circuits
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Solution Overview
Problem
Current integrated circuit testing methods, such as scan tests and boundary scan tests, face inefficiencies due to the complexity and cost associated with using multiple flip-flops for scan elements, which can drive analog and digital circuits incorrectly when incorrect input data are provided, leading to malfunctioning.
Innovation Solution
The integration of a test circuit with storage circuits that inhibit storage of state signals during testing, using a subset of flip-flops marked for storage, and employing a test mode signal to manage scan elements, allowing for efficient loading and reading of data without altering the circuit's operation during normal conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple flip-flops are used for scan elements to test sequential logic circuits, then testing capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the functionality of multiple flip-flops into a single scan element by using a test mode signal to control whether the flip-flop stores state signals or accepts scan input data. This merging reduces the number of storage circuits needed while maintaining testing capability.
Solution Approach 2:
The flip-flop is made dynamic by introducing a test mode signal that changes its behavior based on the testing state. When in test mode, the flip-flop bypasses normal storage functionality and accepts scan input directly, eliminating the need for separate scan flip-flops.
2Productivity
If scan elements are used to load test data into state flip-flops, then testing efficiency is improved, but malfunctioning may occur when incorrect input data are provided
Solution Approach 1:
The patent applies preliminary anti-action by using the test mode signal to prevent incorrect input data from affecting circuit operation. When test mode is active, the flip-flop is configured to accept only scan input data and ignores other inputs, thereby preventing malfunctioning before it can occur.
Solution Approach 2:
The test mode signal acts as an intermediary that mediates between the scan input data and the flip-flop storage element. It controls the connection between the scan input and the flip-flop, ensuring that during testing, only validated test data can be loaded, preventing incorrect data from causing malfunctioning.
3Reliability
If storage circuits are added between state output signals and circuits to prevent malfunctioning, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the storage circuit functionality into the existing state flip-flops by using the test mode signal to control their behavior. This eliminates the need for separate storage circuits while maintaining the ability to prevent malfunctioning during testing.
Solution Approach 2:
The state flip-flops are given multi-functionality by enabling them to operate in both normal mode (storing state signals) and test mode (accepting scan input and preventing malfunctioning). This universal behavior reduces the need for additional dedicated storage circuits.
Data Source
AI summary
An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.