IC Connectivity Testing with Shared Channels and BIST Parallelism

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Solution Overview

Problem

Existing integrated circuit (IC) production testing methods are time-consuming and costly due to the limited parallelism of Automated Test Equipment (ATE) platforms, which are expensive and constrained by the number of tester channels and IC pins.

Innovation Solution

A method and system for IC connectivity testing that utilizes a first and second common test channels connected to non-neighbouring connection elements, combined with Built-In Self-Test (BIST) capability, allowing simultaneous testing of multiple IC pins through multiplexers and internal measurement components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional ATE testing methods are used with one tester channel per pin, then each pin can be tested individually, but the testing process is time-consuming and productivity is low due to limited parallelism

Engineering Contradiction:
Improvetesting speedVSAvoidproduction time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the connection elements into multiple sets (first set, second set, etc.) that can be tested independently through different common test channels. This segmentation allows parallel testing of multiple pins simultaneously, increasing productivity while reducing total production time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces common test channels that can be shared across multiple connection elements. Each common test channel is designed to work with multiple pins through multiplexers, allowing a single test channel to perform multiple testing functions and enabling parallelism without requiring a dedicated channel for each pin.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If more ATE tester channels are used to increase parallelism, then testing efficiency improves, but the cost of ATE platforms increases significantly

Engineering Contradiction:
Improvetesting efficiencyVSAvoidATE platform cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs common test channels that serve multiple connection elements simultaneously. Each common test channel is equipped with multiplexers that allow it to be dynamically connected to different pins during the testing process, enabling a smaller number of expensive ATE channels to achieve the same parallelism that would otherwise require many more channels.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces multiplexers as intermediary components between the common test channels and the connection elements. These multiplexers act as switches that route test signals from a limited number of common channels to multiple pins, enabling parallel testing without requiring a proportional increase in ATE channel count.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If each pin is connected to a dedicated test channel, then testing accuracy is maintained, but the number of required test channels increases, increasing equipment cost and complexity

Engineering Contradiction:
Improvetesting accuracyVSAvoidnumber of test channels
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses multiplexers as intermediary components that maintain signal integrity while enabling shared test channels. These multiplexers ensure that test signals are properly routed and isolated when shared across multiple pins, preserving measurement precision while reducing the total number of required test channels.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the testing process into distinct phases where different sets of connection elements are tested through different common channels. This segmentation ensures that each pin receives dedicated testing attention at its turn, maintaining accuracy while allowing parallel operation across multiple segmented groups.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12510593B2Integrated circuit testing method and system
Publication Date: 2025.12.30 TOUCHNETIX AS
  • US12510593B2 patent drawing
  • US12510593B2 patent drawing
  • US12510593B2 patent drawing

AI summary

Described is a method for connectivity testing of integrated circuits. The method includes connecting an integrated circuit comprising an internal measurement component and a plurality of connection elements to an automated testing apparatus via a first common test channel connected to a first set of non-neighbouring connection elements of the plurality of connection elements and a second common test channel connected to a second set of non-neighbouring connection elements of the plurality of connection elements, different to the first set of non-neighbouring connection elements. The connection elements of the first set of non-neighbouring connection elements neighbour connection elements of the second set of non-neighbouring connection elements. The method further includes connecting a connection element of the plurality of connection elements to the internal measurement component, testing the connected connection element, and identifying a pass or fail for the connected connection element based on the testing.