Integrated Circuit Testing System Using Look-Up Tables
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Solution Overview
Problem
Current methods for testing integrated circuits are time-consuming, leading to delays in the manufacturing process and reduced efficiency in chip development, as they fail to effectively evaluate all parts of the circuitry during the scan test.
Innovation Solution
A testing method and system that converts scan test circuit data into a program to observe untested circuit parts, generates waveform data, and creates a look-up table using a netlist file to test these untested areas, thereby dividing the circuitry into functional regions for targeted testing with optimized patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional scan test methods are used for integrated circuit testing, then the testing procedure is simple and straightforward, but the testing time is excessive and manufacturing process is delayed
Solution Approach 1:
The patent divides the circuitry into multiple functional regions and segments the testing process into multiple stages. The testing circuit identifies untested parts and generates separate test programs for each region, allowing parallel processing and reducing overall testing time while maintaining comprehensive coverage.
Solution Approach 2:
The testing circuit performs preliminary analysis during the scan test to identify untested circuit parts before generating the observation program. This preliminary identification allows the system to prepare targeted test patterns in advance, avoiding retesting and reducing total testing duration.
2Reliability
If traditional scan test methods are used, then the testing procedure is straightforward, but the ability to evaluate all circuit parts is insufficient
Solution Approach 1:
The patent introduces a testing circuit as an intermediary component that bridges the scan test and the observation of untested parts. This testing circuit captures scan test data, identifies untested regions, and generates targeted observation programs, ensuring complete defect evaluation without requiring exhaustive testing of all circuit parts.
Solution Approach 2:
The system implements feedback by using the results of the scan test to dynamically generate the observation program. The testing circuit analyzes which parts were tested and which were not, then automatically creates test patterns for the untested regions, ensuring complete coverage while avoiding redundant testing.
3Reliability
If comprehensive testing of all circuit parts is performed, then defect evaluation is complete, but testing time increases significantly
Solution Approach 1:
The patent applies local quality by generating specialized test patterns tailored to each functional region's characteristics. Instead of using uniform testing approaches, the system analyzes the specific functionality of each circuit region and creates optimized test sequences, improving defect detection accuracy while minimizing testing time for each local area.
Data Source
AI summary
The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.