Integrated Circuit Testing System Using Simulation-Based Pattern Ranking
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Solution Overview
Problem
Current methods for testing integrated circuits are inefficient, requiring extensive time (weeks or months) to evaluate defect devices, thereby reducing the efficiency of chip testing and manufacturing.
Innovation Solution
A testing method and system that utilizes a processor and memory to convert scan test data into a program to observe untested circuitry, perform circuit simulations, rank testing patterns, select candidate patterns, and conduct fault simulations using a netlist file, thereby improving testing efficiency and coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current testing methods are used to evaluate defect devices, then sufficient defect evaluation can be achieved, but the testing time becomes excessively long (weeks or months)
Solution Approach 1:
The patent performs circuit simulations and ranks testing patterns before actual fault simulation to identify and prioritize the most effective test cases. This preliminary ranking allows the system to focus on high-value tests first, significantly reducing the time needed to achieve sufficient defect evaluation coverage.
Solution Approach 2:
The system automatically converts scan test data into a program that observes untested circuitry, performs simulations, ranks patterns, and selects candidate tests without manual intervention. This automated self-service approach eliminates manual testing setup and optimization, drastically reducing testing time while maintaining thorough defect evaluation.
2Productivity
If scan test is performed on circuitry, then testing can be conducted, but untested parts of the circuitry cannot be observed
Solution Approach 1:
The patent introduces an intermediary program that acts as a bridge between scan test data and untested circuitry observation. This program converts scan test data into a form that can observe and analyze previously inaccessible circuit portions, enabling comprehensive coverage without sacrificing testing efficiency.
Solution Approach 2:
The system adds a new dimension to testing by performing circuit simulations that model and observe untested circuitry behavior. This simulation dimension allows the system to infer properties of untested areas, effectively extending test coverage beyond the physical limitations of direct scan testing.
Data Source
AI summary
A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.