IC Thermal Path Structure Through Carrier Substrate Bonding
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Solution Overview
Problem
As technology nodes become smaller, device self-heating becomes an issue due to the removal of the device substrate, which previously provided a thermal path to absorb heat, leading to potential damage of transistor devices.
Innovation Solution
Creating thermal conductive paths from gate terminals of transistor devices to a carrier substrate by patterning bonding oxides and using PN junction structures as reverse diodes to block electrical signals while allowing thermal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the device substrate is removed to enable backside interconnect features, then chip space and power connection efficiency are improved, but thermal management capability deteriorates
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary thermal management solution. The carrier substrate is bonded to the frontside of the thinned circuit structure and provides a thermal path from the transistor devices to the backside of the carrier, enabling heat dissipation without requiring the original device substrate. This mediator resolves the contradiction by providing thermal management capability in the backside configuration.
Solution Approach 2:
The patent transitions the thermal path from a planar configuration to a three-dimensional vertical path. Heat flows vertically from the transistor devices through the frontside interconnect structure and carrier substrate to the backside of the carrier, utilizing the z-dimension for thermal management. This dimensional change enables effective heat dissipation despite the removal of the device substrate.
2Productivity
If the device substrate is removed for backside routing, then power and chip space optimization are achieved, but device reliability deteriorates due to self-heating
Solution Approach 1:
The carrier substrate serves as a mediator that maintains device reliability by providing an alternative thermal path. The frontside interconnect structure and carrier substrate together form a thermal management system that prevents self-heating damage, ensuring device reliability while enabling the benefits of backside routing for power connections and chip space optimization.
Solution Approach 2:
The thermal management function is segmented from the device substrate and implemented through a separate carrier substrate system. This segmentation allows the circuit structure to be thinned and routed on the backside while the carrier substrate independently handles thermal management, maintaining device reliability without compromising power connection efficiency.
3Productivity
If IC dimensions are reduced to improve production efficiency, then manufacturing cost decreases, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by bonding the circuit structure to a carrier substrate and routing interconnect features on the backside. This three-dimensional approach allows continued scaling of IC dimensions in the planar directions while managing complexity through vertical integration and backside processing, maintaining production efficiency despite increased manufacturing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The carrier substrate effectively absorbs heat generated by transistor devices, reducing the risk of damage and improving thermal management in semiconductor structures.
Implementation Method 1
The carrier substrate effectively absorbs heat generated by transistor devices, reducing the risk of damage and improving thermal management in semiconductor structures.
Data Source
AI summary
A semiconductor structure includes a device layer having a transistor device and a PN junction structure coupled to the transistor device. The PN junction structure includes a first doped region and a second doped region, and the first doped region is electrically connected to a gate stack of the transistor device. The semiconductor structure includes a frontside interconnect structure over a frontside of the device layer, the frontside interconnect structure includes thermal path metal features electrically connected to the second doped region of the PN junction structure. The semiconductor structure includes a bonding oxide layer over the frontside interconnect structure, the bonding oxide layer embeds a thermal path metal contact electrically connected to the thermal path metal features. The semiconductor structure includes a carrier substrate over the bonding oxide layer, the carrier substrate landing on a top surface of the thermal path metal contact.