Integrated Circuit Time Budgeting via Module Merging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for time budgeting in integrated circuit design are inefficient and resource-intensive, particularly as complexity increases, leading to excessive computational requirements and differing physical implementations for identical design modules, which complicates the design and manufacturing process.
Innovation Solution
Implementing a method where equal time budgeting is distributed to blocks with the same design module, allowing for simultaneous optimization and ensuring identical time budgets across multiple instances of the same module, thereby reducing computational resources and engineering workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If time budgeting is performed individually for each block in the IC design, then each block can have customized timing specifications, but the computational resource requirements and engineering workloads increase significantly
Solution Approach 1:
The patent merges time budgeting operations for multiple blocks that use the same design module into a single unified process. Instead of performing separate time budgeting for each block instance, the system performs time budgeting once for the design module and applies the results to all instances, thereby reducing computational complexity while maintaining timing specification accuracy.
Solution Approach 2:
The patent creates a universal time budgeting approach where a single time budgeting process serves multiple blocks with identical design modules. The unified time budgeting procedure generates timing specifications that are universally applicable to all instances of a given design module, eliminating the need for separate customized processes while maintaining adaptability.
2Manufacturing precision
If time budgeting is performed individually for each block, then specific timing constraints can be met, but the design process speed and efficiency decrease
Solution Approach 1:
The patent combines multiple individual time budgeting operations into a single unified operation for blocks sharing the same design module. This merging maintains the precision of timing constraint satisfaction while dramatically improving design process speed by eliminating redundant computations across multiple block instances.
3Ease of operation
If different time budgets are assigned to blocks with the same design module, then each block can be optimized independently, but the physical implementations differ requiring additional engineering work
Solution Approach 1:
The patent establishes a universal time budgeting framework where identical design modules receive identical time budgets, ensuring consistent physical implementations across all blocks. This approach maintains ease of operation by allowing independent optimization through the unified process while simultaneously achieving manufacturing consistency by producing identical physical results for identical modules.
4Reliability
If manual re-allocation of block timing constraints is performed to resolve timing issues, then timing requirements can be met, but the engineering workload and time required increase
Solution Approach 1:
The patent performs time budgeting as a preliminary step that automatically establishes correct timing constraints for all blocks before the actual design and optimization processes begin. This preliminary action prevents timing issues from arising in the first place, eliminating the need for subsequent manual re-allocation and reducing engineering workload while ensuring timing requirement fulfillment.
Data Source
AI summary
A method of time budgeting an integrated circuit (IC) including acquiring a graph data structure and clock cycle requirements, where the graph data structure includes at least two identical blocks of a plurality of blocks that correspond to an identical design module. The method acquires internal and external delay values ports of each design module, and sets parameters, which include the internal and external delay values of the at least two identical blocks as equivalent for the identical blocks. The method performs optimization of the parameters of the ports of all of the blocks, and determines whether the optimized parameters of each of the ports satisfy predetermined requirements of the IC. The method outputs a final design of the IC design based on results of the optimization for manufacturing of the IC based on the final design.