Integrated Circuit Timing Analysis via Wire Data
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Solution Overview
Problem
As semiconductor devices are miniaturized, pattern size differences between design and implementation lead to yield degradation, and process variations in metal layers cause timing constraint violations due to increased delays in timing paths, which existing design methods fail to accurately address by lacking consideration of physical wire information during timing analysis.
Innovation Solution
A method and system for designing integrated circuits that generate wire data including layer and physical information of wires, perform timing analysis based on this data, and adjust the layout to account for process variations, thereby improving timing analysis accuracy and addressing design vulnerabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard timing analysis methods are used without considering physical wire information, then the design process is simpler and faster, but timing analysis accuracy deteriorates and timing constraint violations occur due to process variations
Solution Approach 1:
The patent extracts parasitic components from layout data before timing analysis and generates wire data including physical information in advance. This preliminary preparation of accurate wire models (resistance, capacitance, inductance values) enables subsequent timing analysis to account for process variations without adding complexity during the actual timing analysis step.
Solution Approach 2:
The patent introduces wire data as an intermediary element that bridges layout geometry and timing analysis. This wire data structure contains physical information (length, area, resistance, capacitance, inductance) that mediates between the physical layout and the timing analysis engine, enabling accurate delay calculation while keeping the overall process manageable.
2Reliability
If physical wire information and process variations are considered in timing analysis, then timing constraint violations are reduced and chip performance consistency improves, but computational time and resources increase
Solution Approach 1:
The patent changes the parameters used in timing analysis from idealized values to physical measurements including resistance, capacitance, and inductance values that reflect actual process variations. By using corner cases (fast-slow, slow-fast, fast-fast, slow-slow) to represent process variations, the method achieves comprehensive timing verification without requiring exhaustive simulation of every possible variation.
Solution Approach 2:
The patent applies timing analysis to critical paths and significant nets rather than uniformly to all wires in the design. By identifying and focusing computational resources on timing-critical elements (those with large capacitance, resistance, or located on critical timing paths), the method achieves high reliability without the prohibitive computational cost of analyzing every wire in detail.
3Manufacturing precision
If detailed wire data including process variation is extracted and analyzed, then manufacturing precision and yield improve, but the complexity of data processing and analysis increases
Solution Approach 1:
The patent applies different levels of analysis detail to different parts of the design based on their importance. Critical paths and significant nets receive detailed analysis with full process variation consideration, while non-critical elements use simplified models. This local differentiation maintains manufacturing precision for critical elements without overwhelming data processing complexity across the entire design.
4Stability of the object's composition
If timing analysis considers process variation in metal layers, then design robustness improves, but existing design methods become insufficient and more advanced methodologies are required
Solution Approach 1:
The patent segments the timing analysis process into distinct phases: parasitic extraction from layout, wire data generation with physical information, corner case definition for process variations, and timing analysis execution. This segmentation transforms the complex task of variation-aware timing analysis into manageable, sequential steps that can be implemented using existing EDA tools with enhanced capabilities.
Data Source
AI summary
A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.