IC Timing Budgeting via Advanced Factor Path Analysis
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Solution Overview
Problem
As the complexity of integrated circuits increases, existing time budgeting methods become inefficient and inaccurate, leading to a higher likelihood of timing violations during the manufacturing of semiconductor ICs, as they fail to account for advanced timing factors and result in increased engineering and computational resource wastage.
Innovation Solution
A path-based time budgeting method that incorporates advanced timing factors such as clock skew, common path pessimism removal, data cell variation, and signal integrity into the time budgeting algorithm to distribute timing constraints accurately across the entire IC design, optimizing time delay variables to meet clock period requirements and minimize timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time budgeting methods are used for IC design, then the design process is simpler, but timing violation accuracy deteriorates and full-chip timing violations increase
Solution Approach 1:
The patent segments the full-chip timing analysis into individual timing paths, analyzing each path separately to accurately identify timing violations. Instead of treating the entire chip as a single unit, the method divides timing constraints into discrete paths from launch to capture points, enabling precise identification of which specific paths violate timing requirements.
Solution Approach 2:
The patent introduces a new dimension to time budgeting by incorporating spatial information about timing paths across the chip layout. The method analyzes timing constraints not just in terms of time budgets but also in terms of physical path characteristics, adding a spatial dimension to the traditional temporal analysis.
2Reliability
If conventional time budgeting is used, then computational resources are saved, but engineering resource wastage increases due to timing violations
Solution Approach 1:
The patent performs preliminary timing path identification and analysis during the design phase, before finalization. By identifying potential timing violations early through detailed path analysis, the method allows designers to make corrections before manufacturing, preventing costly rework and engineering resource wastage.
Solution Approach 2:
The patent implements a feedback mechanism where timing path analysis results are fed back into the design process. The detailed timing violation information from path analysis provides feedback that guides design modifications, allowing iterative improvement of timing performance while maintaining productivity.
3Measurement precision
If detailed timing path analysis is performed, then timing constraint accuracy improves, but analysis time increases
Solution Approach 1:
The patent extracts and focuses analysis only on critical timing paths that are likely to violate timing constraints, rather than analyzing every possible path in detail. By extracting the most relevant timing paths based on initial screening criteria, the method achieves high accuracy while minimizing computation time.
Solution Approach 2:
The patent applies different levels of analysis detail to different regions and paths based on their timing criticality. Critical paths receive detailed analysis while non-critical paths receive simpler analysis, optimizing the balance between accuracy and computation time through localized quality adjustment.
Data Source
AI summary
A method of time budgeting an integrated circuit (IC) that includes determining an initial value of time delay variables for each block of a plurality of blocks along a set of timing paths based on delays of each design module of the blocks and determining a value of at least one advanced timing factor adjusting a clock period of the IC along each timing path. The method then generates a time budget for ports along each timing path based on the value of the at least one advanced timing factor and the initial value of the time delay variable. The method then optimizes the value of time delay variables by calculating new values of the time delay variables that satisfy each timing path to minimize a possibility of timing violations and to satisfy the clock period of the IC, which is adjusted by the value of the advanced timing factor.