Opportunistic Path Selection for IC Timing Optimization
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Solution Overview
Problem
Traditional physical optimization tools for integrated circuit (IC) design struggle to efficiently identify and optimize bottleneck paths, leading to long run times and impracticality in meeting timing performance goals, especially in circuit designs with many clock groups.
Innovation Solution
An opportunistic candidate path selection method is employed during post-route physical optimization, which compares timing profiles to select paths with negative slack for optimization, allowing for targeted modifications and reducing runtime by focusing on paths that will provide the greatest improvement in timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional physical optimization tools process all paths in a placed and routed circuit design, then timing performance may be improved, but run time becomes excessively long making the tool impractical to use
Solution Approach 1:
The patent segments the set of all timing paths into two categories: critical paths (those with negative slack that violate timing constraints) and non-critical paths. The optimization process focuses exclusively on critical paths, segmenting the problem to avoid processing all paths equally, thereby reducing runtime while maintaining timing performance improvements.
Solution Approach 2:
The patent applies local quality by treating critical paths differently from non-critical paths. Instead of uniform processing, the tool identifies paths with negative slack and applies optimization operations only to these specific paths, giving different treatment quality to different parts of the circuit based on their timing importance.
2Manufacturing precision
If traditional physical optimization tools optimize all paths equally, then comprehensive timing improvement may be achieved, but the complexity of the optimization process increases significantly
Solution Approach 1:
The patent extracts and isolates the critical subset of paths from the complete set of timing paths. By taking out only the paths with negative slack for optimization while leaving non-critical paths unchanged, the method reduces optimization process complexity while still achieving timing closure for the critical bottlenecks.
Solution Approach 2:
The patent applies partial action by optimizing only the necessary subset of critical paths rather than all paths. This partial optimization is sufficient to achieve timing closure for the most problematic paths without incurring the full complexity of comprehensive optimization.
3Productivity
If physical optimization tools focus on selecting and optimizing only critical paths with negative slack, then runtime is reduced and timing performance improves, but the ability to optimize non-critical paths is lost
Solution Approach 1:
The patent implements feedback by iteratively re-evaluating timing paths after optimization operations. Paths that were initially non-critical may become critical after other paths are optimized, and the tool continues to identify and optimize newly emerged critical paths, ensuring comprehensive timing optimization while maintaining efficiency.
Solution Approach 2:
The patent performs preliminary identification of critical paths with negative slack before optimization begins. This preliminary action prioritizes the most critical paths for first optimization, ensuring that the most severe timing violations are addressed first while maintaining the ability to address other paths in subsequent iterations.
Data Source
AI summary
In an example, a method of implementing a circuit design for an integrated circuit (IC) includes: placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths, and executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description.