IC Test Signal Timing Skew Monitoring for Coverage Analysis

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Solution Overview

Problem

Black box testing of IC devices is limited as it does not exhaustively test the internal state, leading to incomplete coverage of signal combinations due to the immense search space, with current methods requiring extensive clock cycles to ensure all scenarios are evaluated.

Innovation Solution

A method involving a test signal generator, a timing skew monitor, and an output monitor to generate and analyze predefined sequences of test signals, monitoring the timing skew between input and output signals to determine executed signal combinations within a predetermined time period, reducing the need to test every possible timing variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If exhaustive black box testing is performed to cover all internal states, then testing completeness is improved, but testing time and complexity increase exponentially

Engineering Contradiction:
Improvetesting completenessVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention changes the testing approach from exhaustive state enumeration to timing-parameter-based testing. By monitoring timing skews between test signals and using histograms to capture timing distributions, the system achieves comprehensive coverage without exponential growth in test cases. The timing parameters (skew values, histograms) replace the need to exhaustively enumerate all internal states.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all possible signal combinations are tested, then signal combination coverage is improved, but the number of test cases increases exponentially

Engineering Contradiction:
Improvesignal combination coverageVSAvoidtest case complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention adds a temporal dimension to signal combination testing by introducing timing skew monitoring. Instead of only checking signal combinations at discrete time points, the system continuously monitors timing relationships between signals and represents them in histograms. This temporal dimension allows comprehensive coverage of signal interactions without exponentially increasing the number of discrete test cases.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If timing variations are exhaustively tested, then timing coverage is improved, but testing resources increase significantly

Engineering Contradiction:
Improvetiming coverageVSAvoidtesting resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system uses self-service by automatically capturing timing information through the timing skew monitor and automatically generating histograms from the captured data. The histograms themselves serve as the testing resource, providing a compact representation of timing variations without requiring extensive external testing resources. The system serves itself by deriving timing coverage metrics directly from operational signal monitoring.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7624323B2Method and apparatus for testing an IC device based on relative timing of test signals
Publication Date: 2009.11.24 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7624323B2 patent drawing
  • US7624323B2 patent drawing
  • US7624323B2 patent drawing

AI summary

An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.