Integrated Circuit Timing Violation Detection
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Solution Overview
Problem
Integrated circuit designs are often classified as defective due to timing slack margins below predetermined limits, failing to account for manufacturing parameter variations, which can lead to unnecessary design adjustments and reduced product yield.
Innovation Solution
A method that evaluates integrated circuit designs by selecting manufacturing parameters of interest, running timing tests, and iteratively calculating timing slack sensitivity to these parameters, adjusting the design to reduce sensitivity to parameters outside acceptable limits, thereby ensuring the design meets timing requirements without pessimistic widening of modeling limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing tests are performed using standard manufacturing specification limits, then the testing process is simple and fast, but timing violations outside specification limits are not detected leading to defective designs being classified as acceptable
Solution Approach 1:
The method performs preliminary timing tests using standard manufacturing specification limits to establish baseline timing slack margins. This preliminary action enables subsequent identification of circuits with low timing slack that may be sensitive to manufacturing variations, allowing targeted re-evaluation without testing all circuits with extended parameters.
Solution Approach 2:
The method applies partial re-evaluation by performing extended parameter timing tests only on circuits identified as having low timing slack margins in the preliminary test. This partial action approach avoids the complexity of testing all circuits with extended parameters while still detecting timing violations outside specification limits for the relevant subset.
2Productivity
If timing slack margin limits are widened to account for manufacturing variations, then more designs are accepted, but the timing requirements become less strict reducing reliability
Solution Approach 1:
The method applies different evaluation criteria to different circuits based on their individual timing slack characteristics. Circuits with high timing slack are evaluated using standard manufacturing limits, while circuits with low timing slack are re-evaluated using extended parameters. This local differentiation maintains reliability for most circuits while improving yield by accepting designs that would otherwise be incorrectly rejected.
Solution Approach 2:
The method changes the timing evaluation parameters from standard manufacturing specification limits to extended parameters that model manufacturing outside specified limits. This parameter change is applied selectively to circuits with low timing slack margins, allowing the system to account for manufacturing variations without universally relaxing timing requirements and maintaining overall reliability.
3Measurement precision
If all timing tests are re-evaluated with extended manufacturing parameters, then timing violations are detected, but the testing time and computational resources increase significantly
Solution Approach 1:
The method performs a preliminary timing test using standard manufacturing specification limits to identify circuits with low timing slack margins. This preliminary screening enables the system to focus extended parameter re-evaluation only on the small subset of circuits that are likely to have timing violations, dramatically reducing the total testing time compared to re-evaluating all circuits.
Solution Approach 2:
The method applies extended parameter timing tests partially, only to circuits identified as having low timing slack in the preliminary test. This partial re-evaluation approach achieves adequate timing violation detection accuracy for the relevant circuits while avoiding the excessive testing time that would result from evaluating all circuits with extended parameters.
Data Source
AI summary
A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.