Latency Measurement in IC Transceivers Using Dual Timing Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Accurately measuring latency in high-speed transceiver channels within integrated circuits is challenging for timestamping protocols like IEEE-1588 and requires deterministic, repeatable, and symmetrical network latency measurements, especially when forward error correction introduces variable delays.
Innovation Solution
A method involving a bitcounter that increments for each data word received, generating both asynchronous and synchronous signals to measure latency by subtracting the time of receipt of these signals, with optional adjustments for asynchronous propagation and bit-position delays, allowing precise latency calculation across various encodings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If latency measurement is performed in high-speed transceiver channels, then synchronization accuracy for timestamping protocols is improved, but measurement precision deteriorates due to variable delays introduced by forward error correction and complex encodings
Solution Approach 1:
The patent introduces intermediary signals (asynchronous start-of-frame indicator and synchronous start-of-frame indicator) that mediate between the transceiver channel and the core logic. These indicators traverse different paths - the asynchronous indicator goes through the full data path including FEC decoding, while the synchronous indicator provides a reference path - allowing measurement of the variable delay introduced by FEC without being affected by it.
Solution Approach 2:
The patent changes the timing parameters by measuring latency at two different reference points: an asynchronous reference point that captures the actual data path delay including FEC processing, and a synchronous reference point that provides a stable timing reference. By comparing these two parameter measurements, the system can compensate for variable delays.
2Reliability
If forward error correction is applied to ensure reliable data transmission, then data integrity is improved, but latency becomes variable and harder to measure accurately
Solution Approach 1:
The patent performs preliminary action by inserting the asynchronous start-of-frame indicator at a known position in the data stream before FEC decoding occurs. This allows the system to capture the timing of the original data arrival and compare it with the timing after FEC processing, thereby measuring the delay introduced by FEC in advance of actual data transmission.
Solution Approach 2:
The patent implements feedback by using the measured latency difference between asynchronous and synchronous indicators to compensate for FEC-induced delays. The system continuously monitors the timing relationship and adjusts timestamp calculations based on the measured delay, creating a closed-loop system that maintains accurate latency measurement despite FEC processing.
3Productivity
If complex encodings are used to increase bandwidth efficiency, then data transmission capacity is improved, but latency measurement accuracy deteriorates due to additional processing delays
Solution Approach 1:
The patent uses start-of-frame indicators as intermediary markers that are inserted into the data stream at a known position before complex encoding and FEC processing. These indicators traverse the entire data path including all encoding and decoding operations, allowing measurement of the total processing delay introduced by complex encodings without affecting the encoding efficiency itself.
Data Source
AI summary
One embodiment relates to a method of performing a latency measurement within an integrated circuit. Receipt of a word that contains a beginning of a frame is detected by a frame begin detect circuit in a decoding circuit block. A begin frame detected signal is fed back to the physical media attachment circuit, and an asynchronous signal from the physical media attachment circuit is transmitted at a beginning of a subsequent frame to a time measurement circuit in a core of the integrated circuit. A bitcount may be used to generate a synchronous signal that is also transmitted to the core. At the core of the integrated circuit, a first time is measured that corresponds to receipt of the asynchronous signal and a second time is measured that corresponds to receipt of the synchronous signal. A latency is determined at least by subtracting the first time subtracted from the second time. Other embodiments and features are also disclosed.