Integrated Circuit Transistor Impurity Segmentation for 1/f Noise Reduction
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Solution Overview
Problem
Miniaturization of transistors in integrated circuits leads to increased 1/f noise due to fluctuations in drain current, which existing technologies have not effectively addressed.
Innovation Solution
The integration circuit employs a combination of high and low concentration transistors, with low concentration transistors used in noise-affected areas and high concentration transistors in driving current stages, along with a shallow trench isolation structure and buried channel type MOSFETs, to reduce mobility fluctuations and drain current noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to increase integration density, then productivity and device complexity are improved, but 1/f noise increases due to mobility fluctuations
Solution Approach 1:
The patent applies different impurity concentrations to different transistor types within the same integrated circuit. Specifically, first transistors (used in differential pairs and current mirror circuits) have lower impurity concentrations in their channel regions to reduce mobility fluctuations and 1/f noise, while second transistors (used in output stages and current sources) have higher impurity concentrations to maintain stable threshold values. This local differentiation resolves the contradiction by optimizing each transistor type for its specific functional requirements.
2Object-affected harmful factors
If impurity concentration in channel regions is lowered to reduce mobility fluctuations, then 1/f noise is reduced, but threshold value stability deteriorates
Solution Approach 1:
The patent implements local quality differentiation by assigning low impurity concentrations to transistors where noise reduction is critical (differential pairs, current mirror circuits) and high impurity concentrations to transistors where threshold stability is critical (output stages, current sources). This resolves the contradiction by ensuring each transistor type operates in its optimal performance regime.
Solution Approach 2:
The patent segments the transistor population into two distinct groups with different impurity concentration characteristics. First transistors are segmented for low-noise applications with lower impurity concentrations, while second transistors are segmented for high-stability applications with higher impurity concentrations. This segmentation allows simultaneous optimization of both noise performance and threshold stability across different circuit blocks.
3Reliability
If different impurity concentrations are used for different transistor types, then noise performance and threshold stability are optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of channel regions for first and second transistors into a single ion implantation process step. By designing the implantation conditions (dose, energy, masking patterns) to simultaneously create the desired impurity concentration profiles for both transistor types, the manufacturing process achieves the differentiated impurity concentrations without requiring separate processing steps, thus minimizing process complexity.
Data Source
AI summary
An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.