IC Trench Plug Architecture for Sub-Resolution Interconnect Pitch
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Solution Overview
Problem
The challenge in integrated circuit (IC) manufacturing is to create conductive traces with extremely small pitches and critical dimensions, which exceeds the resolution capabilities of current lithographic processes, leading to increased costs due to multiple patterning processes.
Innovation Solution
The solution involves forming dielectric plugs and conductive traces using a pitch-splitting patterning technique, where a lithographic plate prints photoresist 'backbone' lines at a given pitch, and then trenches are backfilled with conductive material to achieve traces with reduced pitches and widths on a regular rectangular grid.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic processes are used to pattern conductive traces, then traces can be formed with small dimensions, but the resolution capabilities are insufficient for pitches of 70 nm or less and critical dimensions of 35 nm or less
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete lithographic steps, where each step forms a portion of the final trace pattern. Multiple lithographic masks are used sequentially to build up the complete interconnect structure, allowing each individual patterning step to work within achievable resolution limits while the cumulative effect achieves the target sub-70nm pitch and sub-35nm critical dimension that would be impossible in a single step.
2Manufacturing precision
If multiple lithographic masks are used in a multiple patterning process, then traces with smaller pitches and critical dimensions can be achieved, but IC interconnect costs increase dramatically
Solution Approach 1:
The patent employs preliminary action by performing preparatory steps before the final conductive material deposition. Dielectric plugs are formed in advance at specific locations where trace interruptions are needed, and mandrel structures are created beforehand to guide the subsequent patterning process. These preliminary structures enable the multiple patterning steps to proceed more efficiently and reduce the overall complexity and cost of achieving the required precision.
Solution Approach 2:
The patent uses intermediary elements such as dielectric plugs and mandrel structures that serve as temporary or permanent mediators in the fabrication process. These intermediaries facilitate the transfer of the pattern from lithographic masks to the final conductive trace structure, enabling precise control over trace geometry and interruptions without requiring direct patterning of the conductive material itself at each step.
3Productivity
If cell density in integrated circuits is increased, then circuit functionality is improved, but the spacing between conductive traces must be reduced to extremely small pitches
Solution Approach 1:
The patent addresses the pitch reduction challenge by introducing dimensional complexity through vertical structures (dielectric plugs extending through interconnect layers) and multi-layer interconnect architectures. Rather than relying solely on horizontal trace spacing reduction, the solution utilizes the third dimension (vertical depth) to manage signal routing and isolation, enabling higher cell density without pushing horizontal trace pitches beyond manufacturable limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of complex damascene-type structures at scaled-down geometries, reducing the need for multiple patterning processes and thereby lowering IC interconnect costs while maintaining precise dimensions.
Implementation Method 1
The photoresist layer may be exposed to radiation through a patterned mask
Implementation Method 2
an opening for the trench may be etched in the dielectric layer by using the photoresist layer as an etch mask
Data Source
AI summary
Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in a trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.