Tuning IC Components via Package Distribution Layer Patterns
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Solution Overview
Problem
RF and millimeter-wave integrated circuit design faces inaccuracies due to complex parasitic capacitances and inductances, making it difficult to design precise passive and active circuits like filters, power dividers, and oscillators, with conventional back-end adjustment techniques being time-consuming and limited to transmission lines.
Innovation Solution
A method of tuning inductive and capacitive components by measuring bare-die performance, determining and modifying package distribution layer patterns to achieve desired performance, including ground layer adjustments, without requiring new wafer production, allowing for effective trimming of circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional back-end adjustment techniques are used to improve device performance accuracy, then transmission line performance can be adjusted, but the technique is limited to transmission lines only and cannot effectively tune inductive devices like spiral inductors and transformers
Solution Approach 1:
The patent creates a universal trimming model that can be applied to multiple component types including transmission lines, spiral inductors, and transformers. The model uses a standardized equivalent circuit representation with series resistance, series inductance, parallel capacitance, and parallel resistance parameters that can represent different physical components, allowing the same back-end adjustment technique to tune various component types effectively
2Manufacturing precision
If measurement results are used to re-design and re-optimize inductive devices to compensate for parasitic influences, then device performance accuracy can be improved, but the design cycle is extended by at least one month and additional wafer re-production procedures are required
Solution Approach 1:
The patent incorporates parasitic effect compensation directly into the initial device design and fabrication process. By pre-calculating and pre-compensating for expected parasitic influences during the design phase, and using a universal trimming model that accounts for packaging effects, the system achieves accurate performance without requiring post-measurement redesign iterations, thereby eliminating the one-month delay associated with conventional re-design cycles
Solution Approach 2:
The patent implements a feedback mechanism where initial performance measurements are compared against target specifications, and the universal trimming model is used to calculate precise adjustment parameters. This feedback loop enables rapid determination of ground layer adjustments needed to achieve desired performance, replacing the iterative redesign process with a direct calculation-based correction approach
3Adaptability or versatility
If a universal trimming model is created for wafer-level components, then the model can represent transmission lines, inductors, and transformers, but the packaged component performance differs from wafer-level performance due to packaging effects
Solution Approach 1:
The patent introduces packaging effect compensation as an intermediary layer between the universal trimming model and the actual component performance. The method separately models wafer-level component characteristics and packaging-level parasitic effects, then combines these models to predict final packaged performance. This intermediary compensation approach allows the universal model to remain component-type-agnostic while accurately predicting the actual performance of packaged components
Data Source
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AI summary
A method of tuning inductive and/or capacitive components within an integrated circuit device. The method comprises measuring bare-die mounted performance of such a component formed within a semiconductor die, determining a package distribution layer pattern for the at least one component for achieving a desired performance for the at least one component based at least partly on the measured bare-die mounted performance, and packaging the semiconductor die with the determined package distribution layer pattern for the at least one component.