Automated IC Validation via Polygon Pattern Matching

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Solution Overview

Problem

Current methods for validating integrated circuit (IC) designs after fabrication are time-consuming and prone to errors due to manual inspection and misalignment of cells, leading to inaccuracies in the as-fabricated netlist.

Innovation Solution

An automated circuit design validation system that uses pattern matching circuitry to compare extracted polygon shapes from layer images with a standard cell library, generating a netlist and determining validation metrics by identifying and aligning cells within the images, thereby reducing human error and increasing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual inspection methods are used for IC validation, then human judgment can be applied, but the process is time-consuming and prone to errors

Engineering Contradiction:

Improvevalidation accuracyVSAvoidvalidation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces manual inspection with an automated image processing system that uses computer vision algorithms to identify, extract, and validate IC cells. The system captures images of the IC, processes them through multiple stages (segmentation, feature extraction, cell identification), and generates validation reports automatically, eliminating the need for human inspectors while improving both speed and accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The validation system performs self-validation by automatically comparing extracted cell patterns against a reference database of known IC cell structures. The system independently identifies discrepancies, aligns cells, and generates validation metrics without requiring external human intervention, enabling the process to serve itself.

Inventive Principle:

Principle #25Self-service

2Productivity

If automated pattern matching is implemented, then validation speed increases, but alignment precision must be maintained

Engineering Contradiction:

Improvevalidation throughputVSAvoidcell alignment accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system performs preliminary alignment and normalization of captured IC images before pattern matching. It pre-processes images to correct distortions, standardize orientations, and establish reference frames based on known IC geometry. This preliminary preparation ensures that subsequent automated pattern matching operates on accurately aligned data, maintaining precision while enabling high-speed processing.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system incorporates feedback mechanisms where validation results and alignment measurements are continuously refined. Discrepancies detected during pattern matching trigger iterative adjustment of alignment parameters, and the system uses feedback from successful matches to improve the precision of subsequent matching operations, ensuring high accuracy is maintained throughout the validation process.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20230017484A1Automated circuit design validation

Publication Date: 2023.01.19 BATTELLE MEMORIAL INST

AI summary

The present disclosure provides a circuit design validation system. In one embodiment, the system includes polygon extraction circuitry to determine, based on layer images of a fabricated integrated circuit (IC), a plurality of polygons associated with a layer of the fabricated IC; and cell pattern matching circuitry to search the polygons defined within a layer image of the fabricated IC to determine a match between a cell template of a standard cell library and the plurality of polygons defined within the layer image of the fabricated IC.