Integrated Circuit Verification Apparatus for Dynamic Clock Domain Crossing
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Solution Overview
Problem
Dynamic clock domain crossing verification in integrated circuits often generates pseudo errors due to the inability to distinguish between asynchronous and synchronous data transfers, leading to incorrect identification of issues even when no actual problems exist.
Innovation Solution
A verification apparatus and method that sets a time window for detecting erroneous changes in data signal logic values, excluding a specific period around the clock edge, and determines whether to insert an erroneous sample into a test vector based on the detected transfer type, thereby reducing pseudo errors by accurately simulating metastable phenomena only in asynchronous transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic CDC verification is performed to verify signal transfer between clock domains, then verification coverage is improved, but pseudo errors occur due to inability to distinguish synchronous transfer from asynchronous transfer
Solution Approach 1:
The verification method segments the detection process by dividing the clock cycle into specific time windows. It detects clock edges and sets detection windows that exclude periods around clock edges, thereby segmenting the verification process to distinguish synchronous transfers (which occur during excluded periods) from asynchronous transfers (which occur outside excluded periods), reducing pseudo errors while maintaining verification accuracy
Solution Approach 2:
The method performs preliminary detection of clock edges and pre-establishes detection windows before actual data transfer verification. By preliminarily identifying clock edge positions and setting exclusion periods around them, the system prepares the verification framework in advance to correctly differentiate between synchronous and asynchronous transfers, preventing pseudo error generation
Data Source
AI summary
A method is for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer. The method includes setting a time window for detecting an erroneous change of a logical value of a data signal. The time window ranges a first time period forward and a second time period backward from an edge of a clock signal and excludes a certain sub range. The method includes, during a simulation, determining whether or not the erroneous change of the logical value of the data signal is detected during the set time window. The method includes, upon detection of the erroneous change, inserting an erroneous sample into a test vector for the simulation, and upon non detection of the erroneous change, continuing the simulation without inserting the erroneous sample.