IC Verification Coverage Feedback Loop
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Solution Overview
Problem
Current verification methods for integrated circuit designs, relying on directed and random tests, often fail to comprehensively cover all necessary properties, making it difficult to ensure complete design validation, especially as circuits become more complex.
Innovation Solution
A method that simulates both random and directed test cases, identifies uncovered cover directives, creates properties to fail specifically to cover these directives, and stores simulation traces to ensure thorough verification, thereby enhancing coverage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If random and directed test cases are used for verification, then verification efficiency is improved, but verification coverage is insufficient
Solution Approach 1:
The system monitors simulation results in real-time and uses coverage feedback to dynamically generate new test cases. When a cover directive is not satisfied, the system automatically creates targeted properties and generates additional test vectors to address the specific uncovered area, creating a closed-loop verification process that continuously improves coverage based on actual simulation outcomes
Solution Approach 2:
The system performs preliminary analysis of cover directives before running simulations to identify potential coverage gaps. By pre-processing the design hierarchy and cover directives, the system prepares a framework that enables rapid identification and addressing of uncovered properties during the verification process, reducing the need for extensive random testing
2Reliability
If more test cases are simulated to improve coverage, then verification coverage is improved, but time and effort increase
Solution Approach 1:
The verification process is segmented into hierarchical levels corresponding to different design abstraction levels. Cover directives are organized by hierarchy, and test case generation is focused on specific segments rather than attempting to verify the entire design uniformly. This segmentation allows the system to efficiently target and resolve coverage gaps in specific modules without requiring exhaustive testing of the complete design
Solution Approach 2:
The system dynamically changes test generation parameters based on coverage needs. When coverage gaps are identified, the system adjusts property generation parameters to create targeted test cases that specifically address uncovered directives. This parameter adaptation allows the system to generate fewer but more effective test cases, reducing overall verification time while improving coverage
3Reliability
If manual directed test cases are created to cover specific properties, then verification coverage is improved, but device complexity and effort increase
Solution Approach 1:
The system automatically generates directed test cases without requiring manual intervention. When cover directives are identified as uncovered, the system autonomously creates appropriate properties, generates test vectors, and executes simulations to verify coverage. This self-service capability eliminates the need for manual test case creation while maintaining high verification coverage, reducing both human effort and test case complexity
Data Source
AI summary
A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.