Integrated Circuit Verification Device Exclusion Code Comparison

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Solution Overview

Problem

Existing integrated circuit verification methods struggle to efficiently exclude unverified code caused by the same underlying factors, leading to incomplete verification and potential errors.

Innovation Solution

An integrated circuit verification device and method that includes a condition property information generation unit, an exclusion code generation unit, and an exclusion code comparison unit. These units work together to generate condition properties, exclusion codes, and compare them to efficiently identify and exclude unverified code.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional code coverage methods are used to verify integrated circuit logic, then verification can be performed on the circuit design, but unverified code caused by the same underlying factors cannot be efficiently excluded, leading to incomplete verification

Engineering Contradiction:
Improveverification accuracyVSAvoidunverified code identification
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent segments the verification process into distinct functional units: a condition property information generation unit that creates condition properties from condition statements, an exclusion code generation unit that identifies uncovered code, and an exclusion code comparison unit that compares exclusion codes against condition properties. This segmentation allows systematic tracking and exclusion of unverified code portions, improving verification completeness without redundancy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary generation of condition properties from condition statements before the actual verification process. By pre-defining condition properties that represent expected coverage scenarios, the system can proactively identify and exclude code that should be verified but remains uncovered, preventing incomplete verification results

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive code coverage analysis is performed to ensure complete verification, then verification accuracy improves, but the complexity of managing and analyzing coverage data increases

Engineering Contradiction:
Improveverification accuracyVSAvoidverification system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces condition properties as intermediary elements that mediate between the verification system and the coverage database. These condition properties serve as a structured interface, translating complex coverage requirements into manageable condition statements. This intermediary layer simplifies the management of coverage data while maintaining comprehensive verification capabilities

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transforms coverage analysis from a raw data comparison task into a parameter-based evaluation system. By converting condition statements into structured condition properties with specific parameters, the system changes the nature of the verification process, making it more systematic and easier to manage while improving accuracy

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple condition properties are generated and compared to exclude unverified code, then verification completeness improves, but the processing time and computational resources increase

Engineering Contradiction:
Improveverification completenessVSAvoidverification processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and excludes unverified code portions from the verification process by comparing exclusion codes against condition properties. Once code is identified as excluded through this comparison, it is removed from further verification consideration. This extraction approach prevents redundant processing of the same unverified code segments, reducing overall processing time while maintaining completeness

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12265768B2Integrated circuit verification device, integrated circuit verification method, and non-transitory computer readable medium
Publication Date: 2025.04.01 KIOXIA CORP
  • US12265768B2 patent drawing
  • US12265768B2 patent drawing
  • US12265768B2 patent drawing

AI summary

According to one embodiment, an integrated circuit verification device includes: a condition property information generation unit configured to generate a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file; an exclusion code generation unit configured to generate, from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied; and an exclusion code comparison unit configured to generate a second exclusion code list from a difference between the exclusion code and the first exclusion code list.