Integrated Circuit Verification System Parallel Processing
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Solution Overview
Problem
As semiconductor designs become more integrated and miniaturized, the need for efficient physical verification of integrated circuits increases to reduce defects before mass production, but existing methods are inefficient and expose sensitive design information.
Innovation Solution
A method and system for verifying integrated circuits that perform multiple physical verifications in parallel by merging data on elements and their positions, extracting necessary verification input data, and generating output data, while minimizing information exposure and enhancing security through background data merging and external verification tool interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple physical verifications are performed sequentially using existing methods, then each verification can be completed thoroughly, but the verification time and time-to-fabrication increase significantly
Solution Approach 1:
The verification process is segmented into multiple independent physical verification operations that can be executed in parallel. Each verification tool processes different aspects of the integrated circuit design simultaneously, rather than sequentially, thereby reducing total verification time while maintaining thoroughness of each individual verification.
Solution Approach 2:
Multiple physical verification operations are merged into a unified parallel processing framework. The verification input data is merged and distributed to multiple verification tools that operate concurrently, combining their results to achieve comprehensive verification faster than sequential methods.
2Reliability
If verification data and design information are fully exposed during verification processes, then complete verification can be achieved, but sensitive design information security is compromised
Solution Approach 1:
Only the necessary verification input data is extracted from the complete design information. The system extracts specific portions of design data required for physical verification while leaving sensitive design information embedded in the overall data structure exposed, thereby achieving verification completeness without full information exposure.
Solution Approach 2:
The verification input data acts as an intermediary between the sensitive design information and the verification tools. This intermediary layer provides the necessary data for thorough verification while preventing direct exposure of the underlying sensitive design information to external verification tools.
3Productivity
If verification processes are performed in parallel, then verification speed and time-to-verified-design improve, but system complexity and coordination requirements increase
Solution Approach 1:
The verification system employs universal verification input data that can be processed by multiple different verification tools simultaneously. This multi-functional approach allows the same data structure to serve multiple verification purposes in parallel, improving verification speed while managing system complexity through standardized data interfaces.
Data Source
AI summary
A method of verifying an integrated circuit includes obtaining first data defining elements in the integrated circuit and second data defining positions and connection relationships of the elements, generating chip data by merging the first data and the second data in the background, performing a plurality of physical verifications in parallel, and generating output data, based on results of at least one of physical verifications. The performing of the plurality of physical verifications in parallel includes extracting verification input data used for physical verification, based on the chip data.