IC Physical Design Verification Run Tracking and Machine Selection
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Solution Overview
Problem
Existing physical design verification (PDV) processes for integrated circuits face challenges in efficiently tracking and managing numerous checking runs, leading to inefficiencies in monitoring run statuses, manual data compilation, and delayed submissions, which hinder productivity and design integrity.
Innovation Solution
A computer-implemented method and system for PDV that automates the detection of design changes, predicts suitable execution machines, submits and monitors checking runs, and generates status updates, utilizing a PDV application to streamline the process and reduce manual effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If manual tracking methods (email notifications, physical checking) are used to monitor PDV run statuses, then team members can access run status information, but the process becomes inefficient and time-consuming, leading to delays in accessing critical information
Solution Approach 1:
The patent introduces a web services interface and automated tracking system as an intermediary between the PDV execution environment and team members. This intermediary automatically collects, processes, and distributes run status information through electronic notifications, eliminating the need for manual tracking methods while ensuring timely and accurate information delivery to all stakeholders.
2Loss of information
If a team member manually compiles daily updates on run statuses, then comprehensive status reporting is achieved, but the process becomes highly time-intensive and dependent on team member availability
Solution Approach 1:
The system implements self-service automation where the tracking mechanism automatically queries the PDV execution environment, compiles run status data, and distributes reports without requiring manual intervention. The automated system serves itself by continuously monitoring job statuses and generating updates based on predefined criteria, eliminating the time-intensive manual compilation process while maintaining comprehensive reporting.
Solution Approach 2:
The patent establishes a feedback loop where the automated tracking system continuously monitors PDV run statuses and automatically generates notifications when status changes occur. This feedback mechanism ensures that all team members receive timely updates on run completions, failures, or status changes, maintaining information completeness while eliminating manual reporting efforts.
3Reliability
If numerous checking runs are submitted simultaneously for PDV, then comprehensive verification coverage is achieved, but it becomes challenging to monitor which runs are completed, ongoing, or aborted
Solution Approach 1:
The patent segments the monitoring function into discrete, automated components that track each PDV checking run independently. The system divides the complex monitoring task into individual job status queries, notification generation, and result aggregation steps. This segmentation allows the system to handle numerous simultaneous runs efficiently by processing each run's status separately and consolidating information through automated notifications.
4Loss of information
If traditional manual approaches are used for tracking PDV jobs, then team members can monitor run statuses, but the process leads to delays in accessing critical information and reduced productivity
Solution Approach 1:
The patent replaces manual mechanical tracking methods (email checking, physical log reviews) with an automated electronic tracking system using web services and automated notifications. This substitution eliminates the inefficiencies of manual processes while ensuring timely access to critical PDV information, thereby improving overall design process productivity without sacrificing information accessibility.
Data Source
AI summary
A computer-implemented method for physical design verification (PDV) of a chip includes detecting new data associated with a chip design. The method includes determining differences between previous data associated with the chip design and the detected new data. The method includes determining, based on the differences, checking runs to be submitted for verification of different aspects of the chip. The method includes predicting one or more suitable execution machines for running the checking runs. The method includes identifying a list of available execution machines from the suitable execution machines for executing the checking runs. The method includes submitting the checking runs for execution and monitoring the status of submitted checking runs. The method includes generating a file containing the status of the checking runs.