Integrated Circuit Verification via Network Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit design verification techniques rely on approximations and simplifications, making it computationally exhausting to identify violations of design guidelines, particularly in regards to excessive current density that can lead to electromigration and other functional issues.
Innovation Solution
An integrated circuit design system incorporating a CAD application with a layout extractor, circuit simulator, and electrical rule check module that partitions circuit networks into segments, analyzes current flow, and identifies electromigration violations using detailed simulations and rule checks to ensure compliance with design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional automated design tools are used for verification, then design complexity is managed, but measurement precision of current density and electromigration risks deteriorates due to approximations and simplifications
Solution Approach 1:
The circuit network is partitioned into multiple network segments based on current flow paths and electromigration risks. Each segment is analyzed independently to identify critical areas with excessive current density, enabling precise verification while managing overall complexity through systematic division of the verification task.
Solution Approach 2:
Different verification approaches are applied to different segments of the circuit network based on their specific characteristics and risk levels. High-risk segments with potential electromigration issues receive detailed analysis, while lower-risk segments are verified with appropriate simplifications, optimizing both precision and complexity management.
2Measurement precision
If detailed simulations are performed to accurately evaluate current density, then measurement precision improves, but productivity deteriorates due to computationally exhausting verification processes
Solution Approach 1:
The verification process is divided into segments that are processed in parallel or prioritized based on risk. This allows detailed simulations to be performed only where necessary while maintaining overall verification productivity through efficient task distribution and execution.
Solution Approach 2:
Detailed simulations are performed selectively on critical network segments that pose electromigration risks, rather than performing exhaustive detailed simulations on the entire circuit. This partial action approach maintains measurement precision for critical areas while improving overall productivity by avoiding unnecessary computational resources on lower-risk areas.
3Productivity
If approximations and simplifications are used in verification, then productivity improves, but reliability deteriorates due to inability to accurately identify electromigration violations
Solution Approach 1:
The verification approach applies different levels of detail to different circuit segments based on their reliability importance. Critical segments with high electromigration risk receive rigorous verification to ensure reliability, while less critical segments can be verified with simplified methods, thus maintaining both productivity and reliability.
Solution Approach 2:
The verification process incorporates feedback mechanisms that identify and prioritize segments requiring detailed analysis based on preliminary results. This feedback loop ensures that reliability-critical issues are not missed while maintaining efficient verification processes by focusing detailed analysis only where necessary.
Data Source
AI summary
A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.