IC Signal Line Layout With Vertical Routing Across Cell Boundaries
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing due to limited signal routing flexibility, as the height of circuit cells is constrained by power rails, reducing the number of available horizontal tracks and limiting signal connection options.
Innovation Solution
The use of vertical conducting lines in the second connection layer, overlapping with circuit cells and connected via via-connectors, enhances signal routing flexibility by allowing connections across vertical cell boundaries, thereby improving routing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the height of circuit cells is constrained by power rails, then power distribution is simplified, but signal routing flexibility is reduced
Solution Approach 1:
The patent introduces vertical conducting lines in a second connection layer that extend beyond the horizontal boundaries of circuit cells. This adds a vertical dimension to signal routing, allowing signals to traverse multiple cells vertically rather than being confined to horizontal tracks within each cell. The via-connectors enable transitions between horizontal and vertical routing paths, effectively utilizing the third dimension (vertical space) to overcome the limitations of constrained horizontal routing.
2Volume of moving object
If miniaturization is pursued, then device size is reduced, but signal routing options are limited
Solution Approach 1:
By implementing vertical conducting lines that extend above and below the horizontal plane of circuit cells, the patent creates additional routing pathways in the vertical dimension. This allows signals to route around obstacles and connect distant points without increasing the horizontal footprint of the device, thereby maintaining miniaturization while expanding routing options.
Solution Approach 2:
The vertical conducting lines are positioned to overlap with circuit cells in the horizontal plane while extending in the vertical direction. This nesting arrangement allows the vertical interconnects to pass through the spatial envelope of multiple cells without occupying additional horizontal space, effectively hiding the routing infrastructure within the existing device footprint.
Data Source
AI summary
An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.