Integrated Circuit Vertical Signal Routing
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently routing signals between stacked chips and external circuitry, leading to increased complexity and space requirements, while also struggling with substrate warpage and interconnection reliability.
Innovation Solution
The implementation of a signal distribution layer with contact areas, bond wires, and solder connections that establish continuous connections between the top and bottom faces of integrated circuits, allowing for flexible stacking and reduced footprint, along with the use of package molds to encapsulate and protect contacts, enhancing reliability and reducing substrate warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional signal routing methods are used in stacked integrated circuits, then signal connectivity between chips is achieved, but device complexity and space requirements increase
Solution Approach 1:
The patent transitions from planar signal routing to three-dimensional vertical routing by stacking multiple integrated circuit chips vertically. Signal distribution layers are implemented at different vertical levels (first, second, and third signal distribution layers) to enable signal routing between stacked chips, thereby reducing the footprint and complexity associated with traditional two-dimensional routing while maintaining connectivity.
Solution Approach 2:
The signal routing system is segmented into multiple independent signal distribution layers located at different vertical positions. Each signal distribution layer handles specific signal routing functions, allowing signals to be distributed to different destinations at various stack levels. This segmentation enables independent optimization of each layer's routing paths and reduces overall system complexity.
2Productivity
If more contact pads are placed on the substrate, then interconnection density increases, but substrate warpage worsens
Solution Approach 1:
The patent distributes contact pads across multiple vertical levels rather than concentrating them all on a single substrate plane. Contact pads are provided on the substrate and on different chip layers in the stack, enabling three-dimensional interconnection architecture. This vertical distribution reduces the areal density of contact pads on any single substrate, thereby minimizing warpage while maintaining high overall interconnection density through the stack.
3Length of stationary object
If chip stack height is reduced, then footprint is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment features and registration structures during the chip fabrication process before stacking. Signal distribution layers and contact areas are pre-positioned with precise geometric relationships established during manufacturing. This preliminary positioning ensures that when chips are stacked, the alignment requirements are already satisfied by the pre-established mechanical and electrical feature relationships, reducing the precision demands on the final stacking operation.
4Adaptability or versatility
If bond wires are used for interconnections, then flexibility in routing is improved, but interconnection reliability deteriorates
Solution Approach 1:
The patent merges multiple interconnection methods by combining bond wire connections with direct contact pad connections and solder ball connections. Bond wires provide flexible routing paths for certain signals, while other signals use more reliable direct mechanical and electrical contacts through aligned contact pads across chip interfaces. This hybrid approach combines the routing flexibility of bond wires with the reliability of direct connections, achieving both objectives simultaneously.
Data Source
AI summary
An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad.