IC Interconnection Structure With Protruding Via for Lower Resistance

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Solution Overview

Problem

The via resistance in the via layer of integrated circuit semiconductor devices is high, which affects the performance and reliability of these devices.

Innovation Solution

An interconnection structure is designed with a via layer that includes a protrusion, a barrier film selectively formed on the trench and via layer, and a second conductive layer that fills the trench and is electrically connected to the first conductive layer through the via layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional via structure is used, then the manufacturing process is simple, but the via resistance is high

Engineering Contradiction:
Improvevia resistanceVSAvoidinterconnection structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via layer is extended in the vertical dimension by creating a protrusion that extends above the trench level. This dimensional extension increases the contact area between the via layer and the second conductive layer, thereby reducing via resistance without requiring changes to the fundamental via formation process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The barrier film is selectively formed on the trench surfaces (bottom and sidewalls) before the via layer is deposited. This preliminary action ensures proper adhesion and electrical isolation at the trench-via interfaces, while the via layer is then formed to extend above the trench, combining preventive barrier formation with extended contact area in sequence

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the contact area between via layer and second conductive layer is increased, then via resistance is reduced, but the manufacturing precision requirement increases

Engineering Contradiction:
Improvevia resistanceVSAvoidvia layer formation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via layer is formed to self-align and extend above the trench structure through a single deposition or plating process. The protrusion geometry is determined by the deposition parameters and trench dimensions, allowing the structure to self-organize into the desired configuration without requiring additional alignment steps or complex patterning processes

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The via resistance is reduced by changing the geometric parameters of the via layer, specifically by increasing its height to create a protrusion above the trench. This parameter change (increasing via layer height) directly increases the contact area with the second conductive layer, thereby reducing resistance without requiring changes to material composition or additional processing steps

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12230568B2Interconnection structure of integrated circuit semiconductor device
Publication Date: 2025.02.18 SAMSUNG ELECTRONICS CO LTD
  • US12230568B2 patent drawing
  • US12230568B2 patent drawing
  • US12230568B2 patent drawing

AI summary

An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.