Integrated Circuit Via Layout for Four-Track Standard Cells
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Solution Overview
Problem
The challenge in scaling down integrated circuits is exacerbated by the difficulty in reducing poly pitch, which limits the miniaturization of standard cells due to reduced metal track lines, leading to high pin density, low accessibility, and limited routing resources, thereby restricting cell height to 'five-track' levels.
Innovation Solution
A method involving a semiconductor structure with transistor structures, dielectric separation, and electrically conductive lines and vias, where spacers ensure sufficient distance and aspect ratio for via formation, allowing for the creation of a 'four-track' high standard cell with metal lines along the horizontal axis, enhancing routability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If cell height is reduced to minimize standard cell size, then the number of metal track lines per standard cell is reduced, but routability deteriorates due to high pin density, low pin accessibility, and limited routing resources
Solution Approach 1:
The patent introduces a via structure that extends vertically through the gate plug to connect to the gate electrode, adding a vertical dimension to the interconnect architecture. This allows routing connections to be established through the gate region without requiring additional horizontal metal track lines, thereby maintaining routability while reducing cell height.
Solution Approach 2:
The via structure is nested within the gate plug region, utilizing the vertical space above the gate electrode. The via is formed by etching through the gate plug and filling with conductive material, effectively nesting the interconnect structure within the existing gate architecture to save horizontal space.
2Quantity of substance
If poly pitch is reduced to scale down integrated circuits, then transistor density increases, but manufacturing precision becomes more challenging
Solution Approach 1:
The via formation process is self-aligned to the gate plug structure. The etch process automatically defines the via location based on the gate plug geometry, eliminating the need for separate alignment steps. This self-aligned approach reduces manufacturing complexity and improves precision even as dimensions are scaled down.
3Area of stationary object
If cell height is reduced to five-track level, then standard cell area is minimized, but pin accessibility and routing resources are limited
Solution Approach 1:
The patent utilizes the vertical dimension by forming vias that extend through the gate plug to reach the gate electrode. This vertical interconnect path provides additional routing access points without requiring increased cell height, maintaining pin accessibility while minimizing the standard cell area.
Data Source
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AI summary
Method for forming an integrated circuit comprising the steps of: a. Providing a semiconductor structure comprising: i. two transistors, ii. a gate on the channel of the transistor, iii. contacts coupled to each transistor, iv. a dielectric layer over the two transistors, the gate, and the contacts, v. a first conductive line arranged within a first metallization level and extending along a first direction, vi. a first conductive via connecting the first conductive line with a first contact of a transistor, vii. a second conductive via connecting the first conductive line with a second contact of a transistor, c. recessing the first dielectric layer, d. providing spacers along the first conductive line, e. depositing a second dielectric layer on the first dielectric layer, f. forming an opening in the second and first dielectric material, and g. providing a conductive material in the opening, thereby forming a third conductive via.