Integrated Circuit Via Layout for Lower Resistance Near Gates
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Solution Overview
Problem
As integrated circuits (ICs) continue to scale down, it becomes challenging to balance device reliability with performance, particularly due to increased via resistances which degrade device performance.
Innovation Solution
The proposed solution involves designing via features of varying sizes based on their local environments to optimize performance and minimize shorting risks, while maintaining device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If via features are made smaller to increase functional density, then device integration increases, but via resistance increases and device performance degrades
Solution Approach 1:
The patent applies local quality by making via features adjacent to gate structures smaller to avoid shorting, while making via features in other locations larger to reduce resistance. This spatial variation in via size optimizes both reliability near gates and performance in other regions, resolving the contradiction between functional density and device performance.
2Reliability
If via features are made larger to reduce via resistance, then device performance improves, but risk of shorting with gate structures increases
Solution Approach 1:
The patent implements local quality by differentiating via sizes based on their spatial relationship with gate structures. Vias adjacent to gates are made smaller to eliminate shorting risk, while vias in regions farther from gates are made larger to reduce resistance and improve performance, thus resolving the contradiction between performance and shorting risk.
Solution Approach 2:
The patent introduces dielectric features as intermediaries between via features and gate structures. These dielectric features act as protective barriers that prevent direct contact between enlarged vias and gate structures, allowing vias to be made larger for performance improvement while maintaining reliability by preventing shorting.
3Ease of manufacture
If uniform via size is used throughout the device, then manufacturing simplicity is maintained, but performance optimization is limited
Solution Approach 1:
The patent applies local quality by implementing multiple via size categories (first size for vias adjacent to gates, second size for other vias) to optimize performance in different regions. This approach sacrifices some manufacturing simplicity but achieves significant performance improvement by tailoring via dimensions to local electrical requirements.
Solution Approach 2:
The patent segments the via feature population into distinct groups based on their spatial relationship with gate structures. This segmentation allows different via sizes to be optimized for different functional regions, improving overall device performance while maintaining reasonable manufacturing complexity through systematic classification.
Data Source
AI summary
A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.