IC Via Layout With Local Sizing for Lower Contact Resistance
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Solution Overview
Problem
As IC devices scale down, balancing device reliability and performance becomes challenging due to increased via resistance, particularly in complex structures like memory cells, which affects electrical performance and reliability.
Innovation Solution
Designing via features with varying sizes based on local environments to balance performance and shorting risk, incorporating different via dimensions and conductive line alignments in memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via features are made smaller to reduce shorting risk in scaled-down IC devices, then device reliability improves, but via resistance increases and device performance deteriorates
Solution Approach 1:
The patent applies local quality by making via features adjacent to gate structures smaller to reduce shorting risk, while maintaining larger via dimensions in other regions where shorting risk is lower. This spatial variation in via size optimizes both reliability near gates and electrical performance in less critical areas, resolving the contradiction between reliability and via resistance.
2Productivity
If IC devices are scaled down to increase functional density, then productivity and cost efficiency improve, but via resistance increases and balances between reliability and performance become more challenging
Solution Approach 1:
The patent implements local quality through spatially varying via dimensions that adapt to local environmental factors such as proximity to gate structures. This allows the device to achieve high functional density through scaling while maintaining appropriate via sizes in critical regions to preserve reliability and performance, thus resolving the contradiction between productivity and reliability.
Data Source
AI summary
A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.