IC Individualization Zone Using Random Via Resistance Patterns
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Solution Overview
Problem
Existing methods for individualizing integrated circuits are sensitive to environmental variations and aging, leading to decreased robustness and potential misidentification of legitimate circuits as counterfeit.
Innovation Solution
A method is developed to create a unique individualization zone on microelectronic chips by forming fluorinated residues randomly distributed at via openings, which alters the electrical resistance of certain vias, making each integrated circuit's response diagram unique and stable over time, utilizing a dielectric layer and etching mask process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional dispersions of transistors are used for individualization, then unique identification is achieved, but sensitivity to environmental variations and aging increases
Solution Approach 1:
The patent converts the harmful effect of environmental sensitivity into a beneficial feature by intentionally introducing fluorinated residues that create stable, random variations in via resistance. These controlled variations form a robust individualization signature that is less susceptible to environmental drift compared to transistor-based methods, thereby converting the vulnerability to environmental factors into a stable identification mechanism
Solution Approach 2:
The patent changes the physical-chemical parameters of the via structures by introducing fluorinated residues during the etching process. This modifies the electrical resistance parameter of selected vias, creating a stable individualization pattern that remains consistent across environmental variations and aging, thus improving reliability while reducing environmental sensitivity
2Measurement precision
If contact resistance variations are used for individualization, then unique response times are obtained, but manufacturing precision is compromised
Solution Approach 1:
The patent applies preliminary action by introducing fluorinated residues during the via formation etching process itself, before the conductive material deposition. This preliminary modification ensures that the resistance variations are established at the interface level and remain stable throughout subsequent manufacturing steps, maintaining both measurement precision and manufacturing precision
Solution Approach 2:
The patent applies local quality by selectively introducing fluorinated residues only in specific via openings within the individualization zone, while leaving other vias unaffected. This localized modification creates unique resistance patterns for identification purposes without compromising the overall manufacturing precision of the contact level
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces a Physically Unclonable Function (PUF) zone that is difficult to clone, ensuring each integrated circuit has a unique response and is resistant to environmental changes, thus enhancing authentication and protection against counterfeiting.
Implementation Method 1
forming fluorinated residue randomly distributed at certain via openings, by providing fluorinated species on at least some metal contact zones
Implementation Method 2
The fluorinated residue prevents the electrically conductive material from being correctly deposited in certain openings, in particular by affecting the compliance of the deposition. This fluorinated residue thus leads to the formation of defects in certain vias, at the contact zones. These vias are altered. These altered vias typically have an electrical resistance greater than that of the functional vias.
Data Source
AI summary
The invention is based on a method for producing an individualisation zone of a chip comprising a component level and a contact level comprising vias, the method comprising the following steps:providing the components level and a dielectric layer,forming a mask on the dielectric layer,etching the dielectric layer through mask openings so as to form openings opening onto the contact zones of the components level,forming fluorinated residue by inputting fluorinated species on at least some contact zones, the openings thus comprising openings with fluorinated residue and openings without residue,filling the openings so as to form the vias of the contact level, said vias comprising functional vias at the openings without residue and altered vias at the openings with residue.