Voltage Frequency Balancing Integrated Circuit Timing
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Solution Overview
Problem
Existing integrated circuit design methods often result in non-optimal timing at alternate voltage/frequency pairings due to reliance on nominal targets, limiting the ability to adjust voltage and frequency effectively, especially during varying workloads in VLSI chip operation.
Innovation Solution
A method using statistical static timing analysis (SSTA) to determine optimal voltage/frequency pairs by calculating nominal slack and varying voltage, while solving for frequency within a single clock period, incorporating multi-corner projection to account for process variations and identify correlations among delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If nominal voltage and frequency targets are used for timing analysis, then timing performance at the nominal point is optimized, but timing performance at alternate voltage/frequency pairings becomes non-optimal
Solution Approach 1:
The patent changes the parameters of voltage and frequency from fixed nominal values to variable values across multiple pairings. By analyzing timing at different voltage/frequency pairings and identifying correlations, the system optimizes timing performance across the entire operating range rather than just at a single nominal point.
Solution Approach 2:
The patent performs preliminary timing analysis at multiple voltage/frequency pairings during the design phase to establish correlation models. This preliminary action enables the system to predict and optimize timing performance at alternate pairings without requiring full re-analysis, thus improving adaptability while maintaining precision.
2Adaptability or versatility
If statistical static timing analysis with multiple voltage/frequency pairings is performed, then adaptability and timing optimization across pairings is improved, but computational complexity and analysis time increase
Solution Approach 1:
The patent applies partial action by selecting a representative subset of voltage/frequency pairings for detailed analysis rather than analyzing every possible pairing. By identifying critical paths and correlations at selected pairings, the system extrapolates results to other pairings, reducing analysis time while maintaining optimization effectiveness.
Solution Approach 2:
The patent creates correlation models from timing analysis at selected voltage/frequency pairings and uses these models to predict timing behavior at alternate pairings. This copying approach allows the system to extend optimization results from analyzed pairings to unanalyzed pairings without performing complete re-analysis.
3Ease of operation
If voltage and frequency are adjusted independently, then ease of control is improved, but timing balance and power-performance optimization deteriorates
Solution Approach 1:
The patent introduces dynamic coupling between voltage and frequency control by establishing correlation models that link the two parameters. Instead of independent adjustment, the system adjusts voltage and frequency as coordinated pairs based on timing analysis correlations, maintaining timing balance while enabling flexible optimization across different operating conditions.
Data Source
AI summary
In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.